1# Copyright (c) 2024 Renesas Electronics Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  Renesas RA SDRAM controller.
6  sdram {
7      pinctrl-0 = <&sdram_default>;
8      pinctrl-names = "default";
9      status = "okay";
10      auto-refresh-interval = <10>;
11      auto-refresh-count = <8>;
12      precharge-cycle-count = <3>;
13      multiplex-addr-shift = "10-bit";
14      edian-mode = "little-endian";
15      continuous-access;
16      bus-width = "16-bit";
17      bank@0 {
18        reg = <0>;
19        renesas,ra-sdram-timing = <RENESAS_RA_SDRAM_TRAS_6CYCLES
20                  RENESAS_RA_SDRAM_TRCD_3CYCLES
21                  RENESAS_RA_SDRAM_TRP_3CYCLES
22                  RENESAS_RA_SDRAM_TWR_2CYCLES
23                  RENESAS_RA_SDRAM_TCL_3CYCLES
24                  937
25                  RENESAS_RA_SDRAM_TREFW_8CYCLES>;
26      };
27
28  Note that you will find definitions for the renesas,ra-sdram-control field at
29  dt-bindings/memory-controller/renesas,ra-sdram.h. This file is already included
30  in the SoC DeviceTree files.
31
32  Finally, in order to make the memory available you will need to define new
33  memory device/s in DeviceTree:
34
35  sdram1: sdram@68000000 {
36      compatible = "zephyr,memory-region", "mmio-sram";
37      device_type = "memory";
38      reg = <0x68000000 DT_SIZE_M(X)>;
39      zephyr,memory-region = "SDRAM";
40  };
41
42compatible: "renesas,ra-sdram"
43
44include: [base.yaml, pinctrl-device.yaml]
45
46properties:
47  "#address-cells":
48    required: true
49    const: 1
50
51  "#size-cells":
52    required: true
53    const: 0
54
55  pinctrl-0:
56    required: true
57
58  pinctrl-names:
59    required: true
60
61  auto-refresh-interval:
62    type: int
63    default: 10
64    description: Number of auto-refresh-interval.
65
66  auto-refresh-count:
67    type: int
68    default: 8
69    description: Number of auto-refresh-count.
70
71  precharge-cycle-count:
72    type: int
73    default: 3
74    description: Number of precharge-cycle-count.
75
76  multiplex-addr-shift:
77    type: string
78    default: "10-bit"
79    enum:
80      - "8-bit"
81      - "9-bit"
82      - "10-bit"
83      - "11-bit"
84    description: |
85      Select the size of the shift towards the lower half of the row address in row address/column
86      address multiplexing.
87
88  edian-mode:
89    type: string
90    default: "little-endian"
91    enum:
92      - "little-endian"
93      - "big-endian"
94    description: Specifies the endianness for the SDRAM address space.
95
96  continuous-access:
97    type: boolean
98    description: Enables or disables continuous access to the SDRAM access space.
99
100  bus-width:
101    type: string
102    default: "16-bit"
103    enum:
104      - "16-bit"
105      - "32-bit"
106      - "8-bit"
107    description: Specify the data bus width for SDRAM
108
109child-binding:
110  description: SDRAM bank.
111
112  properties:
113    reg:
114      type: int
115      required: true
116
117    renesas,ra-sdram-timing:
118      type: array
119      required: true
120      description: |
121        SDRAM timing configuration. Expected fields, in order, are,
122
123        - TRAS: Row active interval. The effective value from 1 to 7 cycles
124        - TRCD: Row column latency. The effective value from 1 to 4 cycles
125        - TRP: Row precharge interval. The effective value from 1 to 8 cycles
126        - TWR: Write recovery interval. The effective value from 1 to 2 cycles
127        - TCL: Column latency. The effective value from 1 to 3 cycles
128        - TRFC: Auto-Refresh Request Interval Setting.
129        - TREFW: Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
130          The effective value from 1 to 16 cycles
131