Lines Matching +full:half +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
9 /* 10 Mbit/s transfer with half duplex mask. */
13 /* 100 Mbit/s transfer with half duplex mask. */
28 /* 10 Mbit/s transfer speed with half duplex. */
32 /* 100 Mbit/s transfer speed with half duplex. */
120 /* Port 5 Force Speed control bit */
121 #define P5_SPEED_100M ~BIT(0)
122 /* Port 5 Force Duplex control bit */
123 #define P5_FULL_DUPLEX ~BIT(1)
124 /* Port 5 Force Link control bit. Only available in force mode. */
125 #define P5_FORCE_LINK_ON ~BIT(2)
126 /* Port 5 Force Mode Enable control bit. Only available for
129 #define P5_EN_FORCE BIT(3)
130 /* Bit 4 is reserved and should not be use */
131 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5
134 #define P5_50M_CLK_OUT_ENABLE BIT(5)
135 /* Port 5 Clock Source Selection control bit. Only available when Port 5
138 #define P5_50M_INT_CLK_SOURCE BIT(6)
140 #define P5_NORMAL_SLEW_RATE ~BIT(7)
145 * 100M link fail - LED off
146 * 100M link ok and no TX/RX activity - LED on
147 * 100M link ok and TX/RX activity - LED blinking
149 * No colision: - LED off
150 * Colision: - LED blinking
152 * 10M link fail - LED off
153 * 10M link ok and no TX/RX activity - LED on
154 * 10M link ok and TX/RX activity - LED blinking
156 #define LED_MODE_0 ~(BIT(0) | BIT(1))