1# Copyright 2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  MIPI-DBI Mode C compatible SPI controller. This driver emulates MIPI DBI
6  mode C using a SPI controller and GPIO pins
7compatible: "zephyr,mipi-dbi-spi"
8
9include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
10
11properties:
12  spi-dev:
13    type: phandle
14    required: true
15    description: |
16      SPI device to use for data transfers with MIPI DBI commands. This SPI
17      device should be connected to the MIPI DBI display.
18
19  dc-gpios:
20    type: phandle-array
21    description: |
22      Data/command gpio pin. Required when using 4 wire SPI mode (Mode C1).
23      Set to low when sending a command, or high when sending data.
24
25  reset-gpios:
26    type: phandle-array
27    description: |
28      Reset GPIO pin. Set high to reset the display
29
30  xfr-min-bits:
31    type: int
32    default: 8
33    description:
34      On rare types of SPI interfaces, discrete shift registers can be found
35      whose task is to convert the serial SPI bit stream to the parallel MCU
36      interface with clock and bit accuracy. Typically, these are 16 bits wide.
37
38      Use the macros, not the actual enum value. Here is the concordance list
39      (see dt-bindings/mipi_dbi/mipi_dbi.h)
40         8     MIPI_DBI_SPI_XFR_8BIT
41        16     MIPI_DBI_SPI_XFR_16BIT
42    enum:
43      - 8
44      - 16
45
46  write-only:
47    type: boolean
48    description: |
49      Only writes to display controller, do not perform reads.
50      If all controllers are write-only, read functions will be
51      optimized out for size.
52      It can also be used as an alternative to half duplex when
53      only one data line is connected.
54