Lines Matching +full:half +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
28 #define ADIN2111_RESET_SWRESET BIT(0)
33 #define ADIN2111_CONFIG0_SYNC BIT(15)
35 #define ADIN2111_CONFIG0_TXFCSVE BIT(14)
37 #define ADIN2111_CONFIG0_ZARFE BIT(12)
39 #define ADIN2111_CONFIG0_CSARFE BIT(13)
41 #define ADIN2111_CONFIG0_TXCTE BIT(9)
43 #define ADIN2111_CONFIG0_RXCTE BIT(8)
48 #define ADIN2111_CONFIG2_P2_FWD_UNK2P1 BIT(14)
50 #define ADIN2111_CONFIG2_P1_FWD_UNK2P2 BIT(13)
52 #define ADIN2111_CONFIG2_P2_FWD_UNK2HOST BIT(12)
54 #define ADIN2111_CONFIG2_PORT_CUT_THRU_EN BIT(11)
56 #define ADIN2111_CONFIG2_CRC_APPEND BIT(5)
58 #define ADIN2111_CONFIG2_P1_FWD_UNK2HOST BIT(2)
63 #define ADIN2111_STATUS0_PHYINT BIT(7)
66 * The bit is set when the MACPHY reset is complete
69 #define ADIN2111_STATUS0_RESETC BIT(6)
76 #define ADIN2111_STATUS1_PHYINT BIT(19)
78 #define ADIN2111_STATUS1_P2_RX_RDY BIT(17)
80 #define ADIN2111_STATUS1_SPI_ERR BIT(10)
82 #define ADIN2111_STATUS1_P1_RX_RDY BIT(4)
84 #define ADIN2111_STATUS1_TX_RDY BIT(3)
99 #define ADIN2111_IMASK0_PHYINTM BIT(7)
103 /* Mask Bit for P2_PHYINT */
104 #define ADIN2111_IMASK1_P2_PHYINT_MASK BIT(19)
105 /*!< Mask Bit for P2_RX_RDY. Generic SPI only.*/
106 #define ADIN2111_IMASK1_P2_RX_RDY_MASK BIT(17)
107 /*!< Mask Bit for SPI_ERR. Generic SPI only. */
108 #define ADIN2111_IMASK1_SPI_ERR_MASK BIT(10)
109 /*!< Mask Bit for P1_RX_RDY. Generic SPI only.*/
110 #define ADIN2111_IMASK1_P1_RX_RDY_MASK BIT(4)
111 /*!< Mask Bit for TX_FRM_DONE. Generic SPI only.*/
112 #define ADIN2111_IMASK1_TX_RDY_MASK BIT(3)
121 #define ADIN2111_ADDR_APPLY2PORT2 BIT(31)
122 #define ADIN2111_ADDR_APPLY2PORT1 BIT(30)
123 #define ADIN2111_ADDR_TO_OTHER_PORT BIT(17)
124 #define ADIN2111_ADDR_TO_HOST BIT(16)
175 /* SPI Header for writing control transaction in half duplex mode */
177 /* SPI Header for writing control transaction with MAC TX register (!) in half duplex mode */
179 /* SPI Header for reading control transaction in half duplex mode */
193 /* Max setting to a max RCA of 255 68-bytes ckunks */
198 #define ADIN2111_OA_CTL_MMS BIT(24)
199 #define ADIN2111_OA_CTL_WNR BIT(29)
201 #define ADIN2111_OA_DATA_HDR_DNC BIT(31)
202 #define ADIN2111_OA_DATA_HDR_NORX BIT(29)
204 #define ADIN2111_OA_DATA_HDR_DV BIT(21)
205 #define ADIN2111_OA_DATA_HDR_SV BIT(20)
206 #define ADIN2111_OA_DATA_HDR_EV BIT(14)
209 #define ADIN2111_OA_DATA_FTR_SYNC BIT(29)
211 #define ADIN2111_OA_DATA_FTR_DV BIT(21)
212 #define ADIN2111_OA_DATA_FTR_SV BIT(20)
213 #define ADIN2111_OA_DATA_FTR_EV BIT(14)