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/Zephyr-latest/dts/bindings/pinctrl/
Dpincfg-node.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Generic pin configuration schema
7 Many data items that are represented in a pin configuration node are
8 common and generic. Pin control bindings should use the properties
16 https://www.kernel.org/doc/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
19 bias-disable:
21 description: disable any pin bias
23 bias-high-impedance:
25 description: high impedance mode ("third-state", "floating")
27 bias-bus-hold:
[all …]
Dene,kb1200-pinctrl.yaml1 # SPDX-License-Identifier: Apache-2.0
4 The ENE KB1200 pin controller is a singleton node responsible for controlling
5 pin function selection and pin properties. For example, you can use these
6 nodes to select peripheral pin functions.
8 Here is a list of supported standard pin properties:
9 - bias-disable: Disable pull-up/down resistor.
10 - bias-pull-up: Enable pull-up resistor.
11 - bias-pull-down: Enable pull-down resistor.
12 - drive-push-pull: Output driver is push-pull.
13 - drive-open-drain: Output driver is open-drain.
[all …]
Dmicrochip,xec-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
6 Microchip XEC Pin controller Node
7 Based on pincfg-node.yaml binding.
8 The MCHP XEC pin controller is a singleton node responsible for controlling
9 pin function selection and pin properties. For example, you can use this
10 node to select peripheral pin functions.
19 All device pin configurations should be placed in child nodes of the
22 A group can also specify shared pin properties common to all the specified
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
24 supported standard pin properties:
[all …]
Dmicrochip,mec5-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Microchip XEC Pin controller Node
6 Based on pincfg-node.yaml binding.
7 The MCHP XEC pin controller is a singleton node responsible for controlling
8 pin function selection and pin properties. For example, you can use this
9 node to select peripheral pin functions.
18 All device pin configurations should be placed in child nodes of the
21 A group can also specify shared pin properties common to all the specified
22 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
23 supported standard pin properties:
[all …]
Dnxp,s32k3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32K344-257BGA-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
[all …]
Dti,cc13xx-cc26xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Device pin configuration should be placed in the child nodes of this node.
8 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
18 All device pin configurations should be placed in child nodes of the
22 supported standard pin properties:
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
[all …]
Draspberrypi,pico-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
6 The RPi Pico pin controller is a node responsible for controlling
7 pin function selection and pin properties, such as routing a UART0 Rx
8 to pin 1 and enabling the pullup resistor on that pin.
17 All device pin configurations should be placed in child nodes of the
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
39 /* enable input on pin 1 */
40 input-enable;
[all …]
Dsilabs,dbus-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The Silabs pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties. For example, you can use this
7 node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
8 pin. This pin controller is used for devices that use DBUS (Digital Bus)
15 compatible = "silabs,gecko-usart";
16 pinctrl-0 = <&usart0_default>;
17 pinctrl-names = "default";
20 pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
22 'pinctrl' node, typically in a board-pinctrl.dtsi file in the board
[all …]
Datmel,sam0-pinctrl.yaml2 # Copyright (c) 2021-2022, Gerson Fernando Budke
3 # SPDX-License-Identifier: Apache-2.0
8 The Atmel SAM0 pin controller is a singleton node responsible for controlling
9 pin function selection and pin properties. For example, you can use this node
10 to route SERCOM0 as UART were RX to pin PAD1 and enable the pull-up resistor
11 on the pin.
20 All device pin configurations should be placed in child nodes of the 'pinctrl'
23 /** You can put this in places like a <board>-pinctrl.dtsi file in
27 /** include pre-defined combinations for the SoC variant used by the board */
28 #include <dt-bindings/pinctrl/samr21g-pinctrl.h>
[all …]
Dsilabs,si32-pinctrl.yaml3 # SPDX-License-Identifier: Apache-2.0
8 compatible: "silabs,si32-pinctrl"
11 - name: base.yaml
13 child-binding:
14 description: Si32 pin controller pin group
15 child-binding:
17 Si32 pin controller pin configuration node
20 - name: pincfg-node.yaml
21 property-allowlist:
22 - input-enable
[all …]
Dnxp,port-pinctrl.yaml1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 NXP PORT pinctrl node. This node will define pin configurations in pin
7 group within the pin configuration defines the pin configuration for a
8 peripheral, and each numbered subgroup in the pin group defines all the pins
18 drive-strength = "low";
19 slew-rate = "fast";
23 If only the required properties are supplied, the pin configuration register
28 PCR_SRE=<slew-rate selection>,
29 PCR_DSE=<drive-strength selection>,
[all …]
Dnxp,rt-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 RT600/RT500 pin control node. This node defines pin configurations in pin
7 group within the pin configuration defines a peripheral's pin configuration.
17 slew-rate = "normal";
18 drive-strength = "normal";
24 IOCON_FUNC=<pin mux selection>,
28 IOCON_SLEWRATE = <slew-rate selection>,
29 IOCON_FULLDRIVE = <drive-strength selection>,
35 drive-open-drain: IOCON_ODENA=1
36 bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
[all …]
Dadi,max32-pinctrl.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
5 MAX32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` are default pin configurations.
10 compatible: "adi,max32-pinctrl"
19 child-binding:
24 - name: pincfg-node.yaml
25 property-allowlist:
26 - bias-disable
[all …]
Dnxp,s32ze-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The NXP S32 pin controller is a singleton node responsible for controlling
8 the pin function selection and pin properties. This node, labeled 'pinctrl' in
9 the SoC's devicetree, will define pin configurations in pin groups. Each group
10 within the pin configuration defines the pin configuration for a peripheral,
11 and each numbered subgroup in the pin group defines all the pins for that
20 #include <nxp/s32/S32Z27-BGA594-pinctrl.h>
26 output-enable;
30 input-enable;
35 The 'uart0_default' node contains the pin configurations for a particular state
[all …]
Dquicklogic,eos-s3-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
8 Device pin configuration should be placed in the child nodes of this node.
9 Populate the 'pinmux' field with IO function and pin number.
13 #include <dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
18 input-enable;
22 output-enable;
26 compatible: "quicklogic,eos-s3-pinctrl"
34 child-binding:
40 - name: pincfg-node.yaml
41 property-allowlist:
[all …]
Dnxp,lpc-iocon-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 LPC pinctrl node. This node defines pin configurations in pin groups, and has
7 pin configuration defines a peripheral's pin configuration. Each numbered
16 slew-rate = "standard";
22 IOCON_FUNC=<pin mux selection>,
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
[all …]
/Zephyr-latest/dts/bindings/lora/
Dsemtech,sx127x-base.yaml3 # SPDX-License-Identifier: Apache-2.0
5 include: spi-device.yaml
8 reset-gpios:
9 type: phandle-array
14 This signal is open-drain, active-high (SX1272/3) or
15 active-low (SX1276/7/8/9) as interpreted by the modem.
17 dio-gpios:
18 type: phandle-array
23 These signals are normally active-high.
25 power-amplifier-output:
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_b91.c4 * SPDX-License-Identifier: Apache-2.0
21 ((const struct gpio_b91_config *)dev->config)->gpio_base)
24 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
27 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
29 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
30 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
42 /* Max pin number per port (pin 0..7) */
45 /* IRQ Enable registers */
49 /* Pull-up/down resistors */
69 uint8_t ie; /* IE: input enable, high active. 1: enable, 0: disable */
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dnxp,lpcmp.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP low-power analog comparator (LPCMP)
8 include: [sensor-device.yaml, pinctrl-device.yaml]
17 enable-output-pin:
20 Decide whether to enable the comparator is available in selected pin.
22 use-unfiltered-output:
25 Decide whether to use the unfiltered output.
27 enable-output-invert:
30 Decide whether to invert the comparator output.
32 hysteresis-level:
[all …]
Dbosch,bmi08x-accel.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
14 to output low when produced by the sensor.
16 int1-map-io:
23 int2-map-io:
30 int1-conf-io:
35 Bit[2]: if set to 1, INT1 is open-drain, otherwise it's push-pull
36 Bit[3]: if set to 1, enable INT1 as an output pin
[all …]
/Zephyr-latest/dts/bindings/stepper/adi/
Dadi,trinamic-gconf.yaml1 # SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
2 # SPDX-License-Identifier: Apache-2.0
10 A high level on the pin SPREAD inverts this flag to switch between both chopper modes.
25 sense resistor. VREF pin internally is driven to GND in this mode.
31 1: INDEX output shows step pulses from internal pulse generator (toggle upon each step)
36 0: INDEX output as selected by index_otpw
37 1: INDEX pin shows the current step position of sequencer
54 Enable position compare feature
56 1: Position compare pulse (PP) and interrupt output (INT) are available
59 pull-up or set poscmp_enable=1
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Despressif-esp32-gpio.h4 * SPDX-License-Identifier: Apache-2.0
17 * `DFLT` - The lowest drive strength supported by the HW
18 * `ALT` - The highest drive strength supported by the HW
36 * @name GPIO pin input/output enable flags
38 * These flags allow configuring a pin as input or output while keeping untouched
39 * its complementary configuration. By instance, if we configure a GPIO pin as an
41 * pin's output buffer. This functionality can be useful to render a pin both an
42 * input and output, for diagnose or testing purposes.
47 /** Keep GPIO pin enabled as output */
50 /** Keep GPIO pin enabled as input */
/Zephyr-latest/dts/bindings/comparator/
Dnxp,kinetis-acmp.yaml3 # SPDX-License-Identifier: Apache-2.0
11 compatible = "nxp,kinetis-acmp";
32 pinctrl-0 = <&acmp0_default>;
33 pinctrl-names = "default";
35 positive-mux-input = "IN0";
36 negative-mux-input = "IN1";
39 compatible: "nxp,kinetis-acmp"
42 - base.yaml
43 - pinctrl-device.yaml
52 nxp,enable-output-pin:
[all …]
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_gpio.h2 * Copyright (c) 2016-2017 Piotr Mienkowski
4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Atmel SAM MCU family General Purpose Input Output (GPIO)
19 * Pin flags/attributes
22 /* TODO: replace hard coded pin attribute values with defines provided
62 /** Connect pin to peripheral A. */
64 /** Connect pin to peripheral B. */
66 /** Connect pin to peripheral C. */
68 /** Connect pin to peripheral D. */
70 /** Connect pin to peripheral E. */
[all …]
/Zephyr-latest/boards/microchip/mec172xevb_assy6906/
Dmec172xevb_assy6906.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
26 i2c-0 = &i2c_smb_0;
29 pwm-0 = &pwm0;
34 compatible = "gpio-leds";
53 clock-frequency = <96000000>;
62 /* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */
81 current-speed = <115200>;
82 pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
[all …]

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