1/* 2 * Copyright (c) 2021, Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/dts-v1/; 8 9#include <microchip/mec172xnsz.dtsi> 10#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi> 11 12/ { 13 model = "Microchip MEC172XEVB_ASSY6906 evaluation board"; 14 compatible = "microchip,mec172xevb_assy6906", "microchip,mec172xnsz"; 15 16 chosen { 17 zephyr,sram = &sram0; 18 zephyr,flash = &flash0; 19 zephyr,console = &uart1; 20 }; 21 22 aliases { 23 led0 = &led4; 24 led1 = &led3; 25 i2c0 = &i2c_smb_0; 26 i2c-0 = &i2c_smb_0; 27 i2c1 = &i2c_smb_1; 28 i2c7 = &i2c_smb_2; 29 pwm-0 = &pwm0; 30 watchdog0 = &wdog; 31 }; 32 33 leds { 34 compatible = "gpio-leds"; 35 led4: led_0 { 36 /* GPIO241/CMP_VOUT0/PWM0_ALT on schematic, 37 * LED4 on silkscreen. 38 */ 39 gpios = <MCHP_GPIO_DECODE_241 GPIO_ACTIVE_HIGH>; 40 label = "LED 4"; 41 }; 42 led3: led_1 { 43 /* GPIO175/CMP_VOUT1/PWM8_ALT on schematic, 44 * LED5 on silkscreen. 45 */ 46 gpios = <MCHP_GPIO_DECODE_175 GPIO_ACTIVE_HIGH>; 47 label = "LED 5"; 48 }; 49 }; 50}; 51 52&cpu0 { 53 clock-frequency = <96000000>; 54 status = "okay"; 55}; 56 57/* Initialize ECIA. Does not initialize child devices */ 58&ecia { 59 status = "okay"; 60}; 61 62/* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */ 63&girq24 { 64 status = "okay"; 65}; 66 67&girq25 { 68 status = "okay"; 69}; 70 71&rtimer { 72 status = "okay"; 73}; 74 75&pcr { 76 status = "okay"; 77}; 78 79&uart1 { 80 status = "okay"; 81 current-speed = <115200>; 82 pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; 83 pinctrl-names = "default"; 84}; 85 86&adc0 { 87 status = "okay"; 88 pinctrl-0 = <&adc00_gpio200 &adc03_gpio203 89 &adc04_gpio204 &adc05_gpio205>; 90 pinctrl-1 = <&adc00_gpio200_sleep &adc03_gpio203_sleep 91 &adc04_gpio204_sleep &adc05_gpio205_sleep>; 92 pinctrl-names = "default", "sleep"; 93}; 94 95&espi0 { 96 status = "okay"; 97 pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066 98 &espi_alert_n_gpio063 &espi_clk_gpio065 99 &espi_io0_gpio070 &espi_io1_gpio071 100 &espi_io2_gpio072 &espi_io3_gpio073 >; 101 pinctrl-names = "default"; 102}; 103 104/* enable various eSPI child devices (host facing) */ 105&kbc0 { 106 status = "okay"; 107}; 108 109&acpi_ec0 { 110 status = "okay"; 111}; 112 113&acpi_ec1 { 114 status = "okay"; 115}; 116 117&emi0 { 118 status = "okay"; 119}; 120 121&p80bd0 { 122 status = "okay"; 123}; 124 125/* I2C */ 126&i2c_smb_0 { 127 status = "okay"; 128 port_sel = <0>; 129 130 pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >; 131 pinctrl-names = "default"; 132}; 133 134&i2c00_scl_gpio004 { 135 drive-open-drain; 136 output-enable; 137 output-high; 138}; 139 140&i2c00_sda_gpio003 { 141 drive-open-drain; 142 output-enable; 143 output-high; 144}; 145 146&i2c_smb_1 { 147 status = "okay"; 148 port_sel = <1>; 149 pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>; 150 pinctrl-names = "default"; 151 152 pca9555@26 { 153 compatible = "nxp,pca95xx"; 154 155 /* Depends on JP53 for device address. 156 * Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2. 157 * Address is: 0100<A2><A1><A0>b. 158 * 159 * Default has pin 1-2 on JP53 connected, 160 * resulting in device address 0x26. 161 */ 162 reg = <0x26>; 163 164 gpio-controller; 165 #gpio-cells = <2>; 166 }; 167}; 168 169&i2c01_scl_gpio131 { 170 drive-open-drain; 171 output-enable; 172 output-high; 173}; 174 175&i2c01_sda_gpio130 { 176 drive-open-drain; 177 output-enable; 178 output-high; 179}; 180 181&i2c_smb_2 { 182 status = "okay"; 183 port_sel = <7>; 184 pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>; 185 pinctrl-names = "default"; 186}; 187 188&i2c07_scl_gpio013 { 189 drive-open-drain; 190 output-enable; 191 output-high; 192}; 193 194&i2c07_sda_gpio012 { 195 drive-open-drain; 196 output-enable; 197 output-high; 198}; 199 200&spi0 { 201 status = "okay"; 202 compatible = "microchip,xec-qmspi-ldma"; 203 clock-frequency = <4000000>; 204 lines = <4>; 205 chip-select = <0>; 206 207 pinctrl-0 = < &shd_cs0_n_gpio055 208 &shd_clk_gpio056 209 &shd_io0_gpio223 210 &shd_io1_gpio224 211 &shd_io2_gpio227 212 &shd_io3_gpio016 >; 213 pinctrl-names = "default"; 214}; 215 216&kbd0 { 217 status = "okay"; 218 219 pinctrl-0 = < &ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026 220 &ksi4_gpio027 &ksi5_gpio030 &ksi6_gpio031 &ksi7_gpio032 221 &kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso03_gpio047 222 &kso04_gpio107 &kso05_gpio112 &kso06_gpio113 &kso07_gpio120 223 &kso08_gpio121 &kso09_gpio122 &kso10_gpio123 &kso11_gpio124 224 &kso12_gpio125 &kso13_gpio126 >; 225 pinctrl-1 = < &ksi0_gpio017_sleep &ksi1_gpio020_sleep &ksi2_gpio021_sleep 226 &ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep 227 &ksi6_gpio031_sleep &ksi7_gpio032_sleep &kso00_gpio040_sleep 228 &kso01_gpio045_sleep &kso02_gpio046_sleep &kso03_gpio047_sleep 229 &kso04_gpio107_sleep &kso05_gpio112_sleep &kso06_gpio113_sleep 230 &kso07_gpio120_sleep &kso08_gpio121_sleep &kso09_gpio122_sleep 231 &kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep 232 &kso13_gpio126_sleep >; 233 pinctrl-names = "default", "sleep"; 234 row-size = <8>; 235 col-size = <16>; 236 237 kscan_input: kscan-input { 238 compatible = "zephyr,kscan-input"; 239 }; 240}; 241 242&ksi0_gpio017 { 243 bias-pull-up; 244}; 245 246&ksi1_gpio020 { 247 bias-pull-up; 248}; 249 250&ksi2_gpio021 { 251 bias-pull-up; 252}; 253 254&ksi3_gpio026 { 255 bias-pull-up; 256}; 257 258&ksi4_gpio027 { 259 bias-pull-up; 260}; 261 262&ksi5_gpio030 { 263 bias-pull-up; 264}; 265 266&ksi6_gpio031 { 267 bias-pull-up; 268}; 269 270&ksi7_gpio032 { 271 bias-pull-up; 272}; 273 274&pwm0 { 275 status = "okay"; 276 pinctrl-0 = <&pwm0_gpio053>; 277 pinctrl-names = "default"; 278}; 279 280&tach0 { 281 status = "okay"; 282 pinctrl-0 = <&tach0_gpio050>; 283 pinctrl-names = "default"; 284}; 285 286&ps2_0 { 287 status = "okay"; 288 pinctrl-0 = <&ps2_clk0a_gpio114 &ps2_dat0a_gpio115>; 289 pinctrl-1 = <&ps2_clk0a_gpio114_sleep &ps2_dat0a_gpio115_sleep>; 290 pinctrl-names = "default", "sleep"; 291}; 292 293&timer5 { 294 status = "okay"; 295}; 296