Lines Matching +full:enable +full:- +full:output +full:- +full:pin
1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 NXP PORT pinctrl node. This node will define pin configurations in pin
7 group within the pin configuration defines the pin configuration for a
8 peripheral, and each numbered subgroup in the pin group defines all the pins
18 drive-strength = "low";
19 slew-rate = "fast";
23 If only the required properties are supplied, the pin configuration register
28 PCR_SRE=<slew-rate selection>,
29 PCR_DSE=<drive-strength selection>,
32 compatible: "nxp,port-pinctrl"
36 child-binding:
37 description: NXP PORT pin controller pin group
38 child-binding:
40 NXP PORT pin controller pin configuration node
43 - name: pincfg-node.yaml
44 property-allowlist:
45 - drive-open-drain
46 - bias-pull-up
47 - bias-pull-down
48 - input-enable
55 Pin mux selections for this group. See the soc level pinctrl DTSI file
57 drive-strength:
61 - "low"
62 - "high"
64 Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
65 0 DSE_0- low drive strength when pin is configured as output
66 1 DSE_1- high drive strength when pin is configured as output
67 slew-rate:
70 - "fast"
71 - "slow"
73 Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
74 0 SRE_0_fast- fast slew rate when pin is configured as output
75 1 SRE_1_slow- slow slew rate when pin is configured as output
76 nxp,passive-filter:
79 Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.