1# Copyright 2022-2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  NXP PORT pinctrl node. This node will define pin configurations in pin
6  groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
7  group within the pin configuration defines the pin configuration for a
8  peripheral, and each numbered subgroup in the pin group defines all the pins
9  for that peripheral with the same configuration properties. The 'pins'
10  property in a group selects the pins to be configured, and the remaining
11  properties set configuration values for those pins. Here is an example
12  group for UART0 pins:
13
14  uart0_default: uart0_default {
15    group0 {
16      pins = <UART0_RX_PTB16
17        UART0_TX_PTB17>;
18      drive-strength = "low";
19      slew-rate = "fast";
20      };
21  };
22
23  If only the required properties are supplied, the pin configuration register
24  will be assigned the following values:
25  PCR_PS=0,
26  PCR_PE=0,
27  PCR_ODE=0,
28  PCR_SRE=<slew-rate selection>,
29  PCR_DSE=<drive-strength selection>,
30  PCR_PFE=0
31
32compatible: "nxp,port-pinctrl"
33
34include: base.yaml
35
36child-binding:
37  description: NXP PORT pin controller pin group
38  child-binding:
39    description: |
40      NXP PORT pin controller pin configuration node
41
42    include:
43      - name: pincfg-node.yaml
44        property-allowlist:
45          - drive-open-drain
46          - bias-pull-up
47          - bias-pull-down
48          - input-enable
49
50    properties:
51      pinmux:
52        required: true
53        type: array
54        description: |
55          Pin mux selections for this group. See the soc level pinctrl DTSI file
56          in NXP's HAL for a defined list of these options
57      drive-strength:
58        required: true
59        type: string
60        enum:
61          - "low"
62          - "high"
63        description: |
64          Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
65          0 DSE_0- low drive strength when pin is configured as output
66          1 DSE_1- high drive strength when pin is configured as output
67      slew-rate:
68        type: string
69        enum:
70          - "fast"
71          - "slow"
72        description: |
73          Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
74          0 SRE_0_fast- fast slew rate when pin is configured as output
75          1 SRE_1_slow- slow slew rate when pin is configured as output
76      nxp,passive-filter:
77        type: boolean
78        description: |
79          Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.
80