1# Copyright (c) 2024 Microchip Technology Inc.
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5    Microchip XEC Pin controller Node
6    Based on pincfg-node.yaml binding.
7    The MCHP XEC pin controller is a singleton node responsible for controlling
8    pin function selection and pin properties. For example, you can use this
9    node to select peripheral pin functions.
10
11    The node has the 'pinctrl' node label set in your SoC's devicetree,
12    so you can modify it like this:
13
14      &pinctrl {
15              /* your modifications go here */
16      };
17
18    All device pin configurations should be placed in child nodes of the
19    'pinctrl' node, as in the spi0 example shown at the end:
20
21    A group can also specify shared pin properties common to all the specified
22    pins, such as the 'bias-pull-up' property in group 2. Here is a list of
23    supported standard pin properties:
24
25    - bias-disable: Disable pull-up/down (default behavior, not required).
26    - bias-pull-down: Enable pull-down resistor.
27    - bias-pull-up: Enable pull-up resistor.
28    - drive-push-pull: Output driver is push-pull (default, not required).
29    - drive-open-drain: Output driver is open-drain.
30    - output-high: Set output state high when pin configured.
31    - output-low: Set output state low when pin configured.
32
33    Custom pin properties for drive strength and slew rate are available:
34    - drive-strength
35    - slew-rate
36
37    Driver strength and slew rate hardware defaults vary by SoC and pin.
38
39    An example for MEC174x family, include the chip level pinctrl
40    DTSI file in the board level DTS:
41
42      #include <microchip/mec5/mec1743qlj-a0-pinctrl.dtsi>
43
44    We want to use the shared SPI port of the MEC172x QMSPI controller
45    and want the chip select 0 to be open-drain.
46
47    To change a pin's pinctrl default properties add a reference to the
48    pin in the board's DTS file and set the properties.
49
50      &spi0 {
51        pinctrl-0 = < &shd_cs0_n_gpio055
52                      &shd_clk_gpio056
53                      &shd_io0_gpio223
54                      &shd_io1_gpio224
55                      &shd_io3_gpio016 >;
56        pinctrl-names = "default";
57      }
58
59      &shd_cs0_n_gpio055 {
60        drive-open-drain;
61      };
62
63compatible: "microchip,mec5-pinctrl"
64
65include: base.yaml
66
67properties:
68  reg:
69    required: true
70
71child-binding:
72  description: |
73    This binding gives a base representation of the Microchip XEC pins
74    configuration
75
76  include:
77    - name: pincfg-node.yaml
78      property-allowlist:
79        - bias-disable
80        - bias-pull-down
81        - bias-pull-up
82        - drive-push-pull
83        - drive-open-drain
84        - low-power-enable
85        - output-disable
86        - output-enable
87        - output-high
88        - output-low
89
90  properties:
91    pinmux:
92      type: int
93      required: true
94      description: Pinmux selection
95
96    slew-rate:
97      type: string
98      enum:
99        - "low-speed"
100        - "high-speed"
101      description: |
102        Pin speed. The default value of slew-rate is the SoC power-on-reset
103        value. Please refer to the data sheet as a small number of pins
104        may have a different default and some pins do not implement
105        slew rate adjustment.
106
107    drive-strength:
108      type: string
109      enum:
110        - "1x"
111        - "2x"
112        - "4x"
113        - "6x"
114      description: |
115        Pin output drive strength for PIO and PIO-24 pin types. Default
116        is "1x" for most pins. PIO pins are 2, 4, 8, or 12 mA. PIO-24 pins
117        are 4, 8, 16, or 24 mA. Please refer to the data sheet for each
118        pin's PIO type and default drive strength.
119
120    microchip,output-func-invert:
121      type: boolean
122      description:
123        Invert polarity of an output alternate function. Input functions
124        are not affected.
125