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Searched +full:divider +full:- +full:val (Results 1 – 25 of 51) sorted by relevance

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/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5 * Copyright (c) 2014-2015 Wind River Systems, Inc.
8 * SPDX-License-Identifier: Apache-2.0
18 #define ASSERT_WITHIN_RANGE(val, min, max, str) \ argument
19 BUILD_ASSERT(val >= min && val <= max, str)
21 #define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \ argument
22 BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 || \
23 val == 8 || val == 16 || val == 2 || val == 64, str)
25 #define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val) argument
28 #define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val) argument
[all …]
/Zephyr-latest/drivers/sensor/honeywell/hmc5883l/
Dhmc5883l.c4 * SPDX-License-Identifier: Apache-2.0
21 static void hmc5883l_convert(struct sensor_value *val, int16_t raw_val, in hmc5883l_convert() argument
22 uint16_t divider) in hmc5883l_convert() argument
24 /* val = raw_val / divider */ in hmc5883l_convert()
25 val->val1 = raw_val / divider; in hmc5883l_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in hmc5883l_convert()
31 struct sensor_value *val) in hmc5883l_channel_get() argument
33 struct hmc5883l_data *drv_data = dev->data; in hmc5883l_channel_get()
36 hmc5883l_convert(val, drv_data->x_sample, in hmc5883l_channel_get()
37 hmc5883l_gain[drv_data->gain_idx]); in hmc5883l_channel_get()
[all …]
/Zephyr-latest/drivers/sensor/st/lis3mdl/
Dlis3mdl.c4 * SPDX-License-Identifier: Apache-2.0
21 static void lis3mdl_convert(struct sensor_value *val, int16_t raw_val, in lis3mdl_convert() argument
22 uint16_t divider) in lis3mdl_convert() argument
24 /* val = raw_val / divider */ in lis3mdl_convert()
25 val->val1 = raw_val / divider; in lis3mdl_convert()
26 val->val2 = (((int64_t)raw_val % divider) * 1000000L) / divider; in lis3mdl_convert()
31 struct sensor_value *val) in lis3mdl_channel_get() argument
33 struct lis3mdl_data *drv_data = dev->data; in lis3mdl_channel_get()
37 lis3mdl_convert(val, drv_data->x_sample, in lis3mdl_channel_get()
39 lis3mdl_convert(val + 1, drv_data->y_sample, in lis3mdl_channel_get()
[all …]
/Zephyr-latest/drivers/timer/
Dapic_timer.c3 * SPDX-License-Identifier: Apache-2.0
29 * by the local APIC timer block (before it gets to the timer divider).
34 #define DCR_DIVIDER_MASK 0x0000000F /* divider bits */
71 * away from this roll-over transition by ensuring consecutive CCR in sys_clock_cycle_get_64()
81 return cycles + (CYCLES_PER_TICK - ccr_2nd); in sys_clock_cycle_get_64()
91 uint32_t val; in sys_clock_driver_init() local
94 val = x86_read_loapic(LOAPIC_TIMER_CONFIG); /* set divider */ in sys_clock_driver_init()
95 val &= ~DCR_DIVIDER_MASK; in sys_clock_driver_init()
96 val |= DCR_DIVIDER; in sys_clock_driver_init()
97 x86_write_loapic(LOAPIC_TIMER_CONFIG, val); in sys_clock_driver_init()
[all …]
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c3 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
6 * Copyright (c) 2014-2015 Wind River Systems, Inc.
9 * SPDX-License-Identifier: Apache-2.0
18 #define ASSERT_WITHIN_RANGE(val, min, max, str) \ argument
19 BUILD_ASSERT(val >= min && val <= max, str)
21 #define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \ argument
22 BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 || \
23 val == 8 || val == 16 || val == 2 || val == 64, str)
25 #define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val) argument
28 #define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val) argument
[all …]
/Zephyr-latest/drivers/mdio/
Dmdio_nxp_enet_qos.c4 * SPDX-License-Identifier: Apache-2.0
41 uint32_t val = base->MAC_MDIO_ADDRESS; in check_busy() local
44 return ENET_QOS_REG_GET(MAC_MDIO_ADDRESS, GB, val); in check_busy()
49 enet_qos_t *base = mdio->base; in do_transaction()
53 k_mutex_lock(mdio->mdio_bus_mutex, K_FOREVER); in do_transaction()
55 if (mdio->op == MDIO_OP_C22_WRITE) { in do_transaction()
56 base->MAC_MDIO_DATA = in do_transaction()
58 ENET_QOS_REG_PREP(MAC_MDIO_DATA, GD, mdio->write_data); in do_transaction()
60 } else if (mdio->op == MDIO_OP_C22_READ) { in do_transaction()
63 ret = -EINVAL; in do_transaction()
[all …]
/Zephyr-latest/drivers/sensor/st/lps2xdf/
Dlps2xdf.c6 * SPDX-License-Identifier: Apache-2.0
43 const struct lps2xdf_config *const cfg = dev->config; in lps2xdf_odr_set()
44 const struct lps2xdf_chip_api *chip_api = cfg->chip_api; in lps2xdf_odr_set()
54 return -EINVAL; in lps2xdf_odr_set()
57 if (chip_api->mode_set_odr_raw(dev, odr)) { in lps2xdf_odr_set()
59 return -EIO; in lps2xdf_odr_set()
66 enum sensor_attribute attr, const struct sensor_value *val) in lps2xdf_attr_set() argument
70 return -ENOTSUP; in lps2xdf_attr_set()
75 return lps2xdf_odr_set(dev, val->val1); in lps2xdf_attr_set()
78 return -ENOTSUP; in lps2xdf_attr_set()
[all …]
/Zephyr-latest/dts/bindings/pwm/
Dinfineon,cat1-pwm.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "infineon,cat1-pwm"
10 include: [pwm-controller.yaml, pinctrl-device.yaml]
21 pinctrl-0:
30 pinctrl-0 = <&p1_1_pwm0_0>;
33 pinctrl-names:
39 divider-type:
42 Specifies which type of divider to use.
46 divider-sel:
49 Specifies which divider of the selected type to configure.
[all …]
/Zephyr-latest/samples/basic/fade_led/boards/
Dcyw920829m2evk_02.overlay2 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/pwm/pwm.h>
9 #include <zephyr/dt-bindings/pwm/pwm_ifx_cat1.h>
13 pwm-led0 = &pwm_led0;
17 compatible = "pwm-leds";
27 pinctrl-0 = <&p1_1_pwm0_0>;
28 pinctrl-names = "default";
29 divider-type = <CY_SYSCLK_DIV_16_BIT>;
30 divider-sel = <1>;
31 divider-val = <9599>;
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/Zephyr-latest/drivers/can/
Dcan_sam0.c7 * SPDX-License-Identifier: Apache-2.0
30 int divider; member
33 static int can_sam0_read_reg(const struct device *dev, uint16_t reg, uint32_t *val) in can_sam0_read_reg() argument
35 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_read_reg()
36 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_read_reg()
38 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam0_read_reg()
41 static int can_sam0_write_reg(const struct device *dev, uint16_t reg, uint32_t val) in can_sam0_write_reg() argument
43 const struct can_mcan_config *mcan_config = dev->config; in can_sam0_write_reg()
44 const struct can_sam0_config *sam_config = mcan_config->custom; in can_sam0_write_reg()
49 val = 0; in can_sam0_write_reg()
[all …]
Dcan_sam.c5 * SPDX-License-Identifier: Apache-2.0
27 int divider; member
31 static int can_sam_read_reg(const struct device *dev, uint16_t reg, uint32_t *val) in can_sam_read_reg() argument
33 const struct can_mcan_config *mcan_config = dev->config; in can_sam_read_reg()
34 const struct can_sam_config *sam_config = mcan_config->custom; in can_sam_read_reg()
36 return can_mcan_sys_read_reg(sam_config->base, reg, val); in can_sam_read_reg()
39 static int can_sam_write_reg(const struct device *dev, uint16_t reg, uint32_t val) in can_sam_write_reg() argument
41 const struct can_mcan_config *mcan_config = dev->config; in can_sam_write_reg()
42 const struct can_sam_config *sam_config = mcan_config->custom; in can_sam_write_reg()
44 return can_mcan_sys_write_reg(sam_config->base, reg, val); in can_sam_write_reg()
[all …]
Dcan_numaker.c4 * SPDX-License-Identifier: Apache-2.0
47 const struct can_mcan_config *mcan_config = dev->config; in can_numaker_get_core_clock()
48 const struct can_numaker_config *config = mcan_config->custom; in can_numaker_get_core_clock()
53 clksrc_rate_idx = CLK_GetModuleClockSource(config->clk_modidx); in can_numaker_get_core_clock()
54 /* Module clock divider */ in can_numaker_get_core_clock()
55 clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1; in can_numaker_get_core_clock()
72 return -EIO; in can_numaker_get_core_clock()
75 LOG_DBG("Clock rate index/divider: %d/%d", clksrc_rate_idx, clkdiv_divider); in can_numaker_get_core_clock()
82 const struct can_mcan_config *mcan_config = dev->config; in can_numaker_init_unlocked()
83 const struct can_numaker_config *config = mcan_config->custom; in can_numaker_init_unlocked()
[all …]
/Zephyr-latest/drivers/counter/
Dcounter_renesas_ra_agt.c4 * SPDX-License-Identifier: Apache-2.0
35 timer_source_div_t source_div; /* Clock source divider */
55 /* Alarm-related data */
67 static uint32_t r_agt_ticks_sub(uint32_t val, uint32_t old, uint32_t top);
74 reg->AGTCR = AGT_AGTCR_START_TIMER; in counter_ra_agt_start()
76 while (!(reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) in counter_ra_agt_start()
79 return timeout > 0 ? 0 : -EIO; in counter_ra_agt_start()
87 reg->AGTCR = AGT_AGTCR_STOP_TIMER; in counter_ra_agt_stop()
89 while ((reg->AGTCR & BIT(R_AGTX0_AGT16_CTRL_AGTCR_TCSTF_Pos)) && likely(--timeout)) in counter_ra_agt_stop()
92 return timeout > 0 ? 0 : -EIO; in counter_ra_agt_stop()
[all …]
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.c4 * SPDX-License-Identifier: Apache-2.0
47 * N = input divider value (1, 2, 3 … 15)
48 * M = feedback divider value (4, 5, 6 … 16383)
49 * NO = output divider value (1, 2, 4, or 8)
55 void arc_iot_pll_conf_reg(uint32_t val) in arc_iot_pll_conf_reg() argument
58 sysconf_reg_ptr->CLKSEL = CLKSEL_EXT_16M; in arc_iot_pll_conf_reg()
60 sysconf_reg_ptr->PLLCON = val | (0x52000000); in arc_iot_pll_conf_reg()
62 sysconf_reg_ptr->PLLCON = val | (1 << PLLCON_BIT_OFFSET_PLLRST); in arc_iot_pll_conf_reg()
63 sysconf_reg_ptr->PLLCON = val & (~(1 << PLLCON_BIT_OFFSET_PLLRST)); in arc_iot_pll_conf_reg()
65 while (!(sysconf_reg_ptr->PLLSTAT & (1 << PLLSTAT_BIT_OFFSET_PLLSTB))) { in arc_iot_pll_conf_reg()
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_renesas_cpg_mssr.c2 * Copyright (c) 2020-2022 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
25 void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val) in rcar_cpg_write() argument
27 sys_write32(~val, base_address + CPGWPR); in rcar_cpg_write()
28 sys_write32(val, base_address + reg); in rcar_cpg_write()
63 if (e->module == module) { in cmp_cpg_clk_info_table_items()
65 } else if (e->module < module) { in cmp_cpg_clk_info_table_items()
68 return -1; in cmp_cpg_clk_info_table_items()
75 struct rcar_cpg_mssr_data *data = dev->data; in rcar_cpg_find_clk_info_by_module_id()
[all …]
Dclock_control_r8a7795_cpg_mssr.c6 * SPDX-License-Identifier: Apache-2.0
14 #include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
15 #include <zephyr/dt-bindings/clock/r8a7795_cpg_mssr.h>
82 switch (clk_info->module) { in r8a7795_cpg_enable_disable_core()
87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
105 ret = -ENOTSUP; in r8a7795_cpg_enable_disable_core()
110 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a7795_cpg_enable_disable_core()
119 struct r8a7795_cpg_mssr_data *data = dev->data; in r8a7795_cpg_core_clock_endisable()
[all …]
Dclock_control_litex.c4 * SPDX-License-Identifier: Apache-2.0
66 …* https://github.com/Digilent/Zybo-hdmi-out/blob/b991fff6e964420ae3c00c3dbee52f2ad748b3ba/sdk/disp…
213 return litex_clk_filter_table[glob_mul - 1]; in litex_clk_lookup_filter()
219 return litex_clk_lock_table[glob_mul - 1]; in litex_clk_lookup_lock()
222 static inline void litex_clk_set_reg(uint32_t reg, uint32_t val) in litex_clk_set_reg() argument
224 litex_write(drp[reg].addr, drp[reg].size, val); in litex_clk_set_reg()
234 int assert = (1 << (drp[reg].size * BITS_PER_BYTE)) - 1; in litex_clk_assert_reg()
251 timeout = ldev->timeout.lock; in litex_clk_wait()
253 timeout = ldev->timeout.drdy; in litex_clk_wait()
257 timeout--; in litex_clk_wait()
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h4 * SPDX-License-Identifier: Apache-2.0
20 /** Clock divider */
21 #define STM32_CLOCK_DIV(div) (((div) - 1) << STM32_CLOCK_DIV_SHIFT)
39 * @param val Clock configuration field value (0~0x1F)
44 * @note 'val' range: 0x00~0x1F [ 27 : 31 ]
47 #define STM32_MCO_CFGR(val, mask, shift, reg) \ argument
51 (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT))
54 * Pack RCC clock register offset and bit in two 32-bit values
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
44 #define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) argument
45 #define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) argument
51 /* Numerator of the SYSPLL0 fractional loop divider is 0 */
53 /* Denominator of the SYSPLL0 fractional loop divider is 1 */
61 /* Numerator of the Audio PLL fractional loop divider is 0 */
63 /* Denominator of the Audio PLL fractional loop divider is 1 */
69 .num = 0, .sfg_clock_src = kCLOCK_FrgPllDiv, .divider = 255U, .mult = 0};
[all …]
/Zephyr-latest/samples/boards/nordic/battery/src/
Dbattery.c2 * Copyright (c) 2018-2019 Peter Bigot Consulting, LLC
3 * Copyright (c) 2019-2020 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
27 /* This board uses a divider that reduces max voltage to
46 * the battery is measured through a voltage divider;
85 const struct io_channel_config *iocp = &cfg->io_channel; in divider_setup()
86 const struct gpio_dt_spec *gcp = &cfg->power_gpios; in divider_setup()
88 struct adc_sequence *asp = &ddp->adc_seq; in divider_setup()
89 struct adc_channel_cfg *accp = &ddp->adc_cfg; in divider_setup()
92 if (!device_is_ready(ddp->adc)) { in divider_setup()
[all …]
/Zephyr-latest/drivers/audio/
Dwm8904.c4 * SPDX-License-Identifier: Apache-2.0
28 #define DEV_CFG(dev) ((const struct wm8904_driver_config *const)dev->config)
30 static void wm8904_write_reg(const struct device *dev, uint8_t reg, uint16_t val);
31 static void wm8904_read_reg(const struct device *dev, uint8_t reg, uint16_t *val);
32 static void wm8904_update_reg(const struct device *dev, uint8_t reg, uint16_t mask, uint16_t val);
60 return -EINVAL; in wm8904_protocol_config()
75 uint16_t word_size = cfg->i2s.word_size; in wm8904_audio_fmt_config()
77 switch (cfg->i2s.frame_clk_freq) { in wm8904_audio_fmt_config()
106 LOG_WRN("Invalid codec sample rate: %d", cfg->i2s.frame_clk_freq); in wm8904_audio_fmt_config()
107 return -EINVAL; in wm8904_audio_fmt_config()
[all …]
Dtlv320dac310x.c4 * SPDX-License-Identifier: Apache-2.0
25 #define CODEC_OUTPUT_VOLUME_MIN (-78 * 2)
44 uint8_t val);
46 uint8_t *val);
66 const struct codec_driver_config *const dev_cfg = dev->config; in codec_initialize()
68 if (!device_is_ready(dev_cfg->bus.bus)) { in codec_initialize()
70 return -ENODEV; in codec_initialize()
73 if (!gpio_is_ready_dt(&dev_cfg->reset_gpio)) { in codec_initialize()
75 return -ENODEV; in codec_initialize()
84 const struct codec_driver_config *const dev_cfg = dev->config; in codec_configure()
[all …]
/Zephyr-latest/drivers/watchdog/
Dwdt_mcux_wdog32.c7 * SPDX-License-Identifier: Apache-2.0
44 const struct mcux_wdog32_config *config = dev->config; in mcux_wdog32_setup()
45 struct mcux_wdog32_data *data = dev->data; in mcux_wdog32_setup()
46 WDOG_Type *base = config->base; in mcux_wdog32_setup()
48 if (!data->timeout_valid) { in mcux_wdog32_setup()
50 return -EINVAL; in mcux_wdog32_setup()
53 data->wdog_config.workMode.enableStop = in mcux_wdog32_setup()
56 data->wdog_config.workMode.enableDebug = in mcux_wdog32_setup()
59 WDOG32_Init(base, &data->wdog_config); in mcux_wdog32_setup()
67 const struct mcux_wdog32_config *config = dev->config; in mcux_wdog32_disable()
[all …]
/Zephyr-latest/soc/nuvoton/npcx/common/
Dsoc_clock.h4 * SPDX-License-Identifier: Apache-2.0
38 #define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
39 /* APB1 clock divider */
40 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
41 /* APB2 clock divider */
42 #define APB2DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb2_prescaler) - 1)
43 /* APB3 clock divider */
44 #define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
45 /* APB4 clock divider if supported */
48 #define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
[all …]
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/
Dsoc.c2 * Copyright 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
51 #define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) argument
52 #define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) argument
167 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
168 while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
174 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
228 /* Set SYSCPUAHBCLKDIV divider to value 2 */ in clock_init()
231 /* Set up clock selectors - Attach clocks to the peripheries */ in clock_init()
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