Lines Matching +full:divider +full:- +full:val
2 * Copyright 2020-2023 NXP
4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
51 #define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) argument
52 #define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) argument
167 /* Wait until host_needclk de-asserts */ in usb_device_clock_init()
168 while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) { in usb_device_clock_init()
174 USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; in usb_device_clock_init()
228 /* Set SYSCPUAHBCLKDIV divider to value 2 */ in clock_init()
231 /* Set up clock selectors - Attach clocks to the peripheries */ in clock_init()
235 /* Set PFC0DIV divider to value 2 */ in clock_init()
237 /* Set FRGPLLCLKDIV divider to value 12 */ in clock_init()
277 SYSCTL1->MCLKPINDIR = SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK; in clock_init()
320 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; in clock_init()
321 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; in clock_init()
331 /* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ in clock_init()
341 * Call function flexspi_setup_clock() to set user configured clock source/divider in clock_init()
397 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; in soc_reset_hook()