Lines Matching +full:divider +full:- +full:val
4 * SPDX-License-Identifier: Apache-2.0
25 #define CODEC_OUTPUT_VOLUME_MIN (-78 * 2)
44 uint8_t val);
46 uint8_t *val);
66 const struct codec_driver_config *const dev_cfg = dev->config; in codec_initialize()
68 if (!device_is_ready(dev_cfg->bus.bus)) { in codec_initialize()
70 return -ENODEV; in codec_initialize()
73 if (!gpio_is_ready_dt(&dev_cfg->reset_gpio)) { in codec_initialize()
75 return -ENODEV; in codec_initialize()
84 const struct codec_driver_config *const dev_cfg = dev->config; in codec_configure()
87 if (cfg->dai_type != AUDIO_DAI_TYPE_I2S) { in codec_configure()
89 return -EINVAL; in codec_configure()
93 * de-assert the reset line and thus enable the codec. in codec_configure()
95 gpio_pin_configure_dt(&dev_cfg->reset_gpio, GPIO_OUTPUT_INACTIVE); in codec_configure()
101 ret = codec_configure_dai(dev, &cfg->dai_cfg); in codec_configure()
104 ret = codec_configure_filters(dev, &cfg->dai_cfg); in codec_configure()
146 audio_property_value_t val) in codec_set_property() argument
152 return -EINVAL; in codec_set_property()
157 return codec_set_output_volume(dev, val.vol); in codec_set_property()
160 if (val.mute) { in codec_set_property()
171 return -EINVAL; in codec_set_property()
181 uint8_t val) in codec_write_reg() argument
183 struct codec_driver_data *const dev_data = dev->data; in codec_write_reg()
184 const struct codec_driver_config *const dev_cfg = dev->config; in codec_write_reg()
187 if (dev_data->reg_addr_cache.page != reg.page) { in codec_write_reg()
188 i2c_reg_write_byte_dt(&dev_cfg->bus, 0, reg.page); in codec_write_reg()
189 dev_data->reg_addr_cache.page = reg.page; in codec_write_reg()
192 i2c_reg_write_byte_dt(&dev_cfg->bus, reg.reg_addr, val); in codec_write_reg()
193 LOG_DBG("WR PG:%u REG:%02u VAL:0x%02x", in codec_write_reg()
194 reg.page, reg.reg_addr, val); in codec_write_reg()
198 uint8_t *val) in codec_read_reg() argument
200 struct codec_driver_data *const dev_data = dev->data; in codec_read_reg()
201 const struct codec_driver_config *const dev_cfg = dev->config; in codec_read_reg()
204 if (dev_data->reg_addr_cache.page != reg.page) { in codec_read_reg()
205 i2c_reg_write_byte_dt(&dev_cfg->bus, 0, reg.page); in codec_read_reg()
206 dev_data->reg_addr_cache.page = reg.page; in codec_read_reg()
209 i2c_reg_read_byte_dt(&dev_cfg->bus, reg.reg_addr, val); in codec_read_reg()
210 LOG_DBG("RD PG:%u REG:%02u VAL:0x%02x", in codec_read_reg()
211 reg.page, reg.reg_addr, *val); in codec_read_reg()
222 uint8_t val; in codec_configure_dai() local
225 val = IF_CTRL_IFTYPE(IF_CTRL_IFTYPE_I2S); in codec_configure_dai()
226 if (cfg->i2s.options & I2S_OPT_BIT_CLK_MASTER) { in codec_configure_dai()
227 val |= IF_CTRL_BCLK_OUT; in codec_configure_dai()
230 if (cfg->i2s.options & I2S_OPT_FRAME_CLK_MASTER) { in codec_configure_dai()
231 val |= IF_CTRL_WCLK_OUT; in codec_configure_dai()
234 switch (cfg->i2s.word_size) { in codec_configure_dai()
236 val |= IF_CTRL_WLEN(IF_CTRL_WLEN_16); in codec_configure_dai()
239 val |= IF_CTRL_WLEN(IF_CTRL_WLEN_20); in codec_configure_dai()
242 val |= IF_CTRL_WLEN(IF_CTRL_WLEN_24); in codec_configure_dai()
245 val |= IF_CTRL_WLEN(IF_CTRL_WLEN_32); in codec_configure_dai()
249 cfg->i2s.word_size); in codec_configure_dai()
250 return -EINVAL; in codec_configure_dai()
253 codec_write_reg(dev, IF_CTRL1_ADDR, val); in codec_configure_dai()
266 i2s = &cfg->dai_cfg.i2s; in codec_configure_clocks()
267 LOG_DBG("MCLK %u Hz PCM Rate: %u Hz", cfg->mclk_freq, in codec_configure_clocks()
268 i2s->frame_clk_freq); in codec_configure_clocks()
270 if (cfg->mclk_freq <= DAC_PROC_CLK_FREQ_MAX) { in codec_configure_clocks()
274 ndac = cfg->mclk_freq / DAC_PROC_CLK_FREQ_MAX; in codec_configure_clocks()
277 dac_clk = cfg->mclk_freq / ndac; in codec_configure_clocks()
280 osr_multiple = codec_get_osr_multiple(&cfg->dai_cfg); in codec_configure_clocks()
284 * cfg->i2s.frame_clk_freq and in codec_configure_clocks()
287 osr_min = (DAC_MOD_CLK_FREQ_MIN + i2s->frame_clk_freq - 1) / in codec_configure_clocks()
288 i2s->frame_clk_freq; in codec_configure_clocks()
289 osr_max = DAC_MOD_CLK_FREQ_MAX / i2s->frame_clk_freq; in codec_configure_clocks()
297 mod_clk = i2s->frame_clk_freq * osr; in codec_configure_clocks()
307 osr -= osr_multiple; in codec_configure_clocks()
313 return -EINVAL; in codec_configure_clocks()
320 if (i2s->options & I2S_OPT_BIT_CLK_MASTER) { in codec_configure_clocks()
321 bclk_div = osr * mdac / (i2s->word_size * 2U); /* stereo */ in codec_configure_clocks()
322 if ((bclk_div * i2s->word_size * 2) != (osr * mdac)) { in codec_configure_clocks()
324 i2s->frame_clk_freq * i2s->word_size * 2U, in codec_configure_clocks()
325 cfg->mclk_freq); in codec_configure_clocks()
326 return -EINVAL; in codec_configure_clocks()
341 if (i2s->options & I2S_OPT_BIT_CLK_MASTER) { in codec_configure_clocks()
346 /* calculate MCLK divider to get ~1MHz */ in codec_configure_clocks()
347 mclk_div = DIV_ROUND_UP(cfg->mclk_freq, 1000000); in codec_configure_clocks()
351 LOG_DBG("Timer MCLK Divider: %u", mclk_div); in codec_configure_clocks()
362 if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_192K) { in codec_configure_filters()
365 cfg->i2s.frame_clk_freq); in codec_configure_filters()
366 } else if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_96K) { in codec_configure_filters()
369 cfg->i2s.frame_clk_freq); in codec_configure_filters()
373 cfg->i2s.frame_clk_freq); in codec_configure_filters()
384 if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_192K) { in codec_get_osr_multiple()
386 } else if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_96K) { in codec_get_osr_multiple()
392 LOG_INF("PCM Rate: %u OSR Multiple: %u", cfg->i2s.frame_clk_freq, in codec_get_osr_multiple()
399 uint8_t val; in codec_configure_output() local
405 codec_read_reg(dev, HEADPHONE_DRV_ADDR, &val); in codec_configure_output()
406 val &= ~HEADPHONE_DRV_CM_MASK; in codec_configure_output()
407 val |= HEADPHONE_DRV_CM(CM_VOLTAGE_1P65) | HEADPHONE_DRV_RESERVED; in codec_configure_output()
408 codec_write_reg(dev, HEADPHONE_DRV_ADDR, val); in codec_configure_output()
411 codec_read_reg(dev, HP_OUT_POP_RM_ADDR, &val); in codec_configure_output()
412 codec_write_reg(dev, HP_OUT_POP_RM_ADDR, val | HP_OUT_POP_RM_ENABLE); in codec_configure_output()
415 val = OUTPUT_ROUTING_HPL | OUTPUT_ROUTING_HPR; in codec_configure_output()
416 codec_write_reg(dev, OUTPUT_ROUTING_ADDR, val); in codec_configure_output()
424 /* set headphone outputs as line-out */ in codec_configure_output()
432 codec_read_reg(dev, HEADPHONE_DRV_ADDR, &val); in codec_configure_output()
433 val |= HEADPHONE_DRV_POWERUP | HEADPHONE_DRV_RESERVED; in codec_configure_output()
434 codec_write_reg(dev, HEADPHONE_DRV_ADDR, val); in codec_configure_output()
449 return -EINVAL; in codec_set_output_volume()
453 vol = -vol; in codec_set_output_volume()
478 uint8_t val; in codec_read_all_regs() local
480 codec_read_reg(dev, SOFT_RESET_ADDR, &val); in codec_read_all_regs()
481 codec_read_reg(dev, NDAC_DIV_ADDR, &val); in codec_read_all_regs()
482 codec_read_reg(dev, MDAC_DIV_ADDR, &val); in codec_read_all_regs()
483 codec_read_reg(dev, OSR_MSB_ADDR, &val); in codec_read_all_regs()
484 codec_read_reg(dev, OSR_LSB_ADDR, &val); in codec_read_all_regs()
485 codec_read_reg(dev, IF_CTRL1_ADDR, &val); in codec_read_all_regs()
486 codec_read_reg(dev, BCLK_DIV_ADDR, &val); in codec_read_all_regs()
487 codec_read_reg(dev, OVF_FLAG_ADDR, &val); in codec_read_all_regs()
488 codec_read_reg(dev, PROC_BLK_SEL_ADDR, &val); in codec_read_all_regs()
489 codec_read_reg(dev, DATA_PATH_SETUP_ADDR, &val); in codec_read_all_regs()
490 codec_read_reg(dev, VOL_CTRL_ADDR, &val); in codec_read_all_regs()
491 codec_read_reg(dev, L_DIG_VOL_CTRL_ADDR, &val); in codec_read_all_regs()
492 codec_read_reg(dev, DRC_CTRL1_ADDR, &val); in codec_read_all_regs()
493 codec_read_reg(dev, L_BEEP_GEN_ADDR, &val); in codec_read_all_regs()
494 codec_read_reg(dev, R_BEEP_GEN_ADDR, &val); in codec_read_all_regs()
495 codec_read_reg(dev, BEEP_LEN_MSB_ADDR, &val); in codec_read_all_regs()
496 codec_read_reg(dev, BEEP_LEN_MIB_ADDR, &val); in codec_read_all_regs()
497 codec_read_reg(dev, BEEP_LEN_LSB_ADDR, &val); in codec_read_all_regs()
499 codec_read_reg(dev, HEADPHONE_DRV_ADDR, &val); in codec_read_all_regs()
500 codec_read_reg(dev, HP_OUT_POP_RM_ADDR, &val); in codec_read_all_regs()
501 codec_read_reg(dev, OUTPUT_ROUTING_ADDR, &val); in codec_read_all_regs()
502 codec_read_reg(dev, HPL_ANA_VOL_CTRL_ADDR, &val); in codec_read_all_regs()
503 codec_read_reg(dev, HPR_ANA_VOL_CTRL_ADDR, &val); in codec_read_all_regs()
504 codec_read_reg(dev, HPL_DRV_GAIN_CTRL_ADDR, &val); in codec_read_all_regs()
505 codec_read_reg(dev, HPR_DRV_GAIN_CTRL_ADDR, &val); in codec_read_all_regs()
506 codec_read_reg(dev, HEADPHONE_DRV_CTRL_ADDR, &val); in codec_read_all_regs()
508 codec_read_reg(dev, TIMER_MCLK_DIV_ADDR, &val); in codec_read_all_regs()