Lines Matching +full:divider +full:- +full:val

3  * Copyright (c) 2019-2021 Vestas Wind Systems A/S
6  * Copyright (c) 2014-2015 Wind River Systems, Inc.
9  * SPDX-License-Identifier: Apache-2.0
18 #define ASSERT_WITHIN_RANGE(val, min, max, str) \  argument
19 	BUILD_ASSERT(val >= min && val <= max, str)
21 #define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \  argument
22 	BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 ||	\
23 		     val == 8 || val == 16 || val == 2 || val == 64, str)
25 #define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val)  argument
28 #define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)  argument
35 		    "Invalid SCG bus clock divider value");
37 		    "Invalid SCG core clock divider value");
51 		       "Invalid SCG SIRC divider 2 value");
66 		       "Invalid SCG FIRC divider 2 value");