7  * SPDX-License-Identifier: Apache-2.0
30 	int divider;  member
33 static int can_sam0_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)  in can_sam0_read_reg()  argument
35 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam0_read_reg()
36 	const struct can_sam0_config *sam_config = mcan_config->custom;  in can_sam0_read_reg()
38 	return can_mcan_sys_read_reg(sam_config->base, reg, val);  in can_sam0_read_reg()
41 static int can_sam0_write_reg(const struct device *dev, uint16_t reg, uint32_t val)  in can_sam0_write_reg()  argument
43 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam0_write_reg()
44 	const struct can_sam0_config *sam_config = mcan_config->custom;  in can_sam0_write_reg()
49 		val = 0;  in can_sam0_write_reg()
53 		val = CAN_MCAN_ILE_EINT0;  in can_sam0_write_reg()
60 	return can_mcan_sys_write_reg(sam_config->base, reg, val);  in can_sam0_write_reg()
65 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam0_read_mram()
66 	const struct can_sam0_config *sam_config = mcan_config->custom;  in can_sam0_read_mram()
68 	return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len);  in can_sam0_read_mram()
74 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam0_write_mram()
75 	const struct can_sam0_config *sam_config = mcan_config->custom;  in can_sam0_write_mram()
77 	return can_mcan_sys_write_mram(sam_config->mram, offset, src, len);  in can_sam0_write_mram()
82 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam0_clear_mram()
83 	const struct can_sam0_config *sam_config = mcan_config->custom;  in can_sam0_clear_mram()
85 	return can_mcan_sys_clear_mram(sam_config->mram, offset, len);  in can_sam0_clear_mram()
96 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_sam0_get_core_clock()
97 	const struct can_sam0_config *sam_cfg = mcan_cfg->custom;  in can_sam0_get_core_clock()
101 	*rate = SOC_ATMEL_SAM0_DFLL48_FREQ_HZ / (sam_cfg->divider);  in can_sam0_get_core_clock()
104 	*rate = SOC_ATMEL_SAM0_OSC48M_FREQ_HZ / (sam_cfg->divider);  in can_sam0_get_core_clock()
115 	GCLK->GENCTRL[7].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL)  in can_sam0_clock_enable()
116 			     | GCLK_GENCTRL_DIV(cfg->divider)  in can_sam0_clock_enable()
120 	GCLK->GENCTRL[7].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M)  in can_sam0_clock_enable()
121 			     | GCLK_GENCTRL_DIV(cfg->divider)  in can_sam0_clock_enable()
126 	GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK7  in can_sam0_clock_enable()
130 	*cfg->mclk |= cfg->mclk_mask;  in can_sam0_clock_enable()
135 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_sam0_init()
136 	const struct can_sam0_config *sam_cfg = mcan_cfg->custom;  in can_sam0_init()
141 	ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);  in can_sam0_init()
147 	ret = can_mcan_configure_mram(dev, 0U, sam_cfg->mram);  in can_sam0_init()
159 	sam_cfg->config_irq();  in can_sam0_init()
217 		.divider = DT_INST_PROP(inst, divider),					\