2  * Copyright 2022-2023, NXP
4  * SPDX-License-Identifier: Apache-2.0
11  * This module provides routines to initialize and support board-level
44 #define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val)  argument
45 #define TO_CLOCK_ATTACH_ID(inst, val)     CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val)  argument
51 	/* Numerator of the SYSPLL0 fractional loop divider is 0 */
53 	/* Denominator of the SYSPLL0 fractional loop divider is 1 */
61 	/* Numerator of the Audio PLL fractional loop divider is 0 */
63 	/* Denominator of the Audio PLL fractional loop divider is 1 */
69 	.num = 0, .sfg_clock_src = kCLOCK_FrgPllDiv, .divider = 255U, .mult = 0};
72 	.num = 12, .sfg_clock_src = kCLOCK_FrgMainClk, .divider = 255U, .mult = 167};
176 	/*  Wait until host_needclk de-asserts */  in usb_device_clock_init()
177 	while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) {  in usb_device_clock_init()
183 	USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;  in usb_device_clock_init()
203 	MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;  in soc_reset_hook()
236 	/* Let CPU run on FRO with divider 2 for safe switching. */  in rt5xx_clock_init()
262 	/* Set SYSCPUAHBCLKDIV divider to value 2 */  in rt5xx_clock_init()
270 	/* Set up clock selectors - Attach clocks to the peripheries. */  in rt5xx_clock_init()
333 	/* Note- pixel clock follows formula  in rt5xx_clock_init()
335 	 * this means the clock divider will vary depending on  in rt5xx_clock_init()
352 	/* Enable write-through for FlexSPI1 space */  in rt5xx_clock_init()
353 	CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U;  in rt5xx_clock_init()
354 	CACHE64_POLSEL0->POLSEL = 0x11U;  in rt5xx_clock_init()
389 	/* Set AUDIOPLLCLKDIV divider to value 15 */  in rt5xx_clock_init()
391 	/* Set FRGPLLCLKDIV divider to value 11 */  in rt5xx_clock_init()
393 	/* Set SYSTICKFCLKDIV divider to value 2 */  in rt5xx_clock_init()
395 	/* Set PFC0DIV divider to value 2 */  in rt5xx_clock_init()
397 	/* Set PFC1DIV divider to value 4 */  in rt5xx_clock_init()
399 	/* Set CLKOUTFCLKDIV divider to value 100 */  in rt5xx_clock_init()
404 	 * Call function flexspi_setup_clock() to set user configured clock source/divider  in rt5xx_clock_init()
423 	SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK;  in rt5xx_clock_init()
424 	SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK;  in rt5xx_clock_init()
434 	/* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ  in rt5xx_clock_init()
453 	SYSCTL1->MCLKPINDIR = SYSCTL1_MCLKPINDIR_MCLKPINDIR_MASK;  in rt5xx_clock_init()
482 	 * We set the divider of the PFD3 output of the SYSPLL, which has a  in imxrt_pre_init_display_interface()
539 	/* Some ROM versions may have errata leaving these pins in a non-reset state,  in soc_early_init_hook()
543 	IOPCTL->PIO[1][15] = 0;  in soc_early_init_hook()
544 	IOPCTL->PIO[3][28] = 0;  in soc_early_init_hook()
545 	IOPCTL->PIO[3][29] = 0;  in soc_early_init_hook()