1 /*
2 * Copyright (c) 2022 Vestas Wind Systems A/S
3 * Copyright (c) 2021 Alexander Wachter
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/can.h>
9 #include <zephyr/drivers/can/can_mcan.h>
10 #include <zephyr/drivers/pinctrl.h>
11 #include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
12 #include <soc.h>
13 #include <zephyr/kernel.h>
14 #include <zephyr/logging/log.h>
15 #include <zephyr/irq.h>
16
17 LOG_MODULE_REGISTER(can_sam, CONFIG_CAN_LOG_LEVEL);
18
19 #define DT_DRV_COMPAT atmel_sam_can
20
21 struct can_sam_config {
22 mm_reg_t base;
23 mem_addr_t mram;
24 void (*config_irq)(void);
25 const struct atmel_sam_pmc_config clock_cfg;
26 const struct pinctrl_dev_config *pcfg;
27 int divider;
28 mm_reg_t dma_base;
29 };
30
can_sam_read_reg(const struct device * dev,uint16_t reg,uint32_t * val)31 static int can_sam_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
32 {
33 const struct can_mcan_config *mcan_config = dev->config;
34 const struct can_sam_config *sam_config = mcan_config->custom;
35
36 return can_mcan_sys_read_reg(sam_config->base, reg, val);
37 }
38
can_sam_write_reg(const struct device * dev,uint16_t reg,uint32_t val)39 static int can_sam_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
40 {
41 const struct can_mcan_config *mcan_config = dev->config;
42 const struct can_sam_config *sam_config = mcan_config->custom;
43
44 return can_mcan_sys_write_reg(sam_config->base, reg, val);
45 }
46
can_sam_read_mram(const struct device * dev,uint16_t offset,void * dst,size_t len)47 static int can_sam_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
48 {
49 const struct can_mcan_config *mcan_config = dev->config;
50 const struct can_sam_config *sam_config = mcan_config->custom;
51
52 return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len);
53 }
54
can_sam_write_mram(const struct device * dev,uint16_t offset,const void * src,size_t len)55 static int can_sam_write_mram(const struct device *dev, uint16_t offset, const void *src,
56 size_t len)
57 {
58 const struct can_mcan_config *mcan_config = dev->config;
59 const struct can_sam_config *sam_config = mcan_config->custom;
60
61 return can_mcan_sys_write_mram(sam_config->mram, offset, src, len);
62 }
63
can_sam_clear_mram(const struct device * dev,uint16_t offset,size_t len)64 static int can_sam_clear_mram(const struct device *dev, uint16_t offset, size_t len)
65 {
66 const struct can_mcan_config *mcan_config = dev->config;
67 const struct can_sam_config *sam_config = mcan_config->custom;
68
69 return can_mcan_sys_clear_mram(sam_config->mram, offset, len);
70 }
71
can_sam_get_core_clock(const struct device * dev,uint32_t * rate)72 static int can_sam_get_core_clock(const struct device *dev, uint32_t *rate)
73 {
74 const struct can_mcan_config *mcan_cfg = dev->config;
75 const struct can_sam_config *sam_cfg = mcan_cfg->custom;
76
77 *rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider);
78
79 return 0;
80 }
81
can_sam_clock_enable(const struct can_sam_config * sam_cfg)82 static void can_sam_clock_enable(const struct can_sam_config *sam_cfg)
83 {
84 REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1);
85 PMC->PMC_SCER |= PMC_SCER_PCK5;
86
87 /* Enable CAN clock in PMC */
88 (void)clock_control_on(SAM_DT_PMC_CONTROLLER,
89 (clock_control_subsys_t)&sam_cfg->clock_cfg);
90 }
91
can_sam_init(const struct device * dev)92 static int can_sam_init(const struct device *dev)
93 {
94 const struct can_mcan_config *mcan_cfg = dev->config;
95 const struct can_sam_config *sam_cfg = mcan_cfg->custom;
96 int ret;
97
98 can_sam_clock_enable(sam_cfg);
99
100 ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);
101 if (ret < 0) {
102 return ret;
103 }
104
105 /* get actual message ram base address */
106 uint32_t mrba = sam_cfg->mram & 0xFFFF0000;
107
108 /* keep lower 16bit; update DMA Base Register */
109 sys_write32((sys_read32(sam_cfg->dma_base) & 0x0000FFFF) | mrba, sam_cfg->dma_base);
110
111 ret = can_mcan_configure_mram(dev, mrba, sam_cfg->mram);
112 if (ret != 0) {
113 return ret;
114 }
115
116 ret = can_mcan_init(dev);
117 if (ret != 0) {
118 return ret;
119 }
120
121 sam_cfg->config_irq();
122
123 return ret;
124 }
125
126 static DEVICE_API(can, can_sam_driver_api) = {
127 .get_capabilities = can_mcan_get_capabilities,
128 .start = can_mcan_start,
129 .stop = can_mcan_stop,
130 .set_mode = can_mcan_set_mode,
131 .set_timing = can_mcan_set_timing,
132 .send = can_mcan_send,
133 .add_rx_filter = can_mcan_add_rx_filter,
134 .remove_rx_filter = can_mcan_remove_rx_filter,
135 .get_state = can_mcan_get_state,
136 #ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
137 .recover = can_mcan_recover,
138 #endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
139 .get_core_clock = can_sam_get_core_clock,
140 .get_max_filters = can_mcan_get_max_filters,
141 .set_state_change_callback = can_mcan_set_state_change_callback,
142 .timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
143 .timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
144 #ifdef CONFIG_CAN_FD_MODE
145 .set_timing_data = can_mcan_set_timing_data,
146 .timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
147 .timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
148 #endif /* CONFIG_CAN_FD_MODE */
149 };
150
151 static const struct can_mcan_ops can_sam_ops = {
152 .read_reg = can_sam_read_reg,
153 .write_reg = can_sam_write_reg,
154 .read_mram = can_sam_read_mram,
155 .write_mram = can_sam_write_mram,
156 .clear_mram = can_sam_clear_mram,
157 };
158
159 #define CAN_SAM_IRQ_CFG_FUNCTION(inst) \
160 static void config_can_##inst##_irq(void) \
161 { \
162 LOG_DBG("Enable CAN##inst## IRQ"); \
163 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, int0, irq), \
164 DT_INST_IRQ_BY_NAME(inst, int0, priority), can_mcan_line_0_isr, \
165 DEVICE_DT_INST_GET(inst), 0); \
166 irq_enable(DT_INST_IRQ_BY_NAME(inst, int0, irq)); \
167 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(inst, int1, irq), \
168 DT_INST_IRQ_BY_NAME(inst, int1, priority), can_mcan_line_1_isr, \
169 DEVICE_DT_INST_GET(inst), 0); \
170 irq_enable(DT_INST_IRQ_BY_NAME(inst, int1, irq)); \
171 }
172
173 #define CAN_SAM_CFG_INST(inst) \
174 CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, can_sam_cbs_##inst); \
175 CAN_MCAN_DT_INST_MRAM_DEFINE(inst, can_sam_mram_##inst); \
176 \
177 static const struct can_sam_config can_sam_cfg_##inst = { \
178 .base = CAN_MCAN_DT_INST_MCAN_ADDR(inst), \
179 .mram = (mem_addr_t)POINTER_TO_UINT(&can_sam_mram_##inst), \
180 .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(inst), \
181 .divider = DT_INST_PROP(inst, divider), \
182 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
183 .config_irq = config_can_##inst##_irq, \
184 .dma_base = (mm_reg_t) DT_INST_REG_ADDR_BY_NAME(inst, dma_base) \
185 }; \
186 \
187 static const struct can_mcan_config can_mcan_cfg_##inst = \
188 CAN_MCAN_DT_CONFIG_INST_GET(inst, &can_sam_cfg_##inst, \
189 &can_sam_ops, \
190 &can_sam_cbs_##inst);
191
192 #define CAN_SAM_DATA_INST(inst) \
193 static struct can_mcan_data can_mcan_data_##inst = \
194 CAN_MCAN_DATA_INITIALIZER(NULL);
195
196 #define CAN_SAM_DEVICE_INST(inst) \
197 CAN_DEVICE_DT_INST_DEFINE(inst, can_sam_init, NULL, \
198 &can_mcan_data_##inst, \
199 &can_mcan_cfg_##inst, \
200 POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
201 &can_sam_driver_api);
202
203 #define CAN_SAM_INST(inst) \
204 CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(inst); \
205 PINCTRL_DT_INST_DEFINE(inst); \
206 CAN_SAM_IRQ_CFG_FUNCTION(inst) \
207 CAN_SAM_CFG_INST(inst) \
208 CAN_SAM_DATA_INST(inst) \
209 CAN_SAM_DEVICE_INST(inst)
210
211 DT_INST_FOREACH_STATUS_OKAY(CAN_SAM_INST)
212
