5  * SPDX-License-Identifier: Apache-2.0
27 	int divider;  member
31 static int can_sam_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)  in can_sam_read_reg()  argument
33 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam_read_reg()
34 	const struct can_sam_config *sam_config = mcan_config->custom;  in can_sam_read_reg()
36 	return can_mcan_sys_read_reg(sam_config->base, reg, val);  in can_sam_read_reg()
39 static int can_sam_write_reg(const struct device *dev, uint16_t reg, uint32_t val)  in can_sam_write_reg()  argument
41 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam_write_reg()
42 	const struct can_sam_config *sam_config = mcan_config->custom;  in can_sam_write_reg()
44 	return can_mcan_sys_write_reg(sam_config->base, reg, val);  in can_sam_write_reg()
49 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam_read_mram()
50 	const struct can_sam_config *sam_config = mcan_config->custom;  in can_sam_read_mram()
52 	return can_mcan_sys_read_mram(sam_config->mram, offset, dst, len);  in can_sam_read_mram()
58 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam_write_mram()
59 	const struct can_sam_config *sam_config = mcan_config->custom;  in can_sam_write_mram()
61 	return can_mcan_sys_write_mram(sam_config->mram, offset, src, len);  in can_sam_write_mram()
66 	const struct can_mcan_config *mcan_config = dev->config;  in can_sam_clear_mram()
67 	const struct can_sam_config *sam_config = mcan_config->custom;  in can_sam_clear_mram()
69 	return can_mcan_sys_clear_mram(sam_config->mram, offset, len);  in can_sam_clear_mram()
74 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_sam_get_core_clock()
75 	const struct can_sam_config *sam_cfg = mcan_cfg->custom;  in can_sam_get_core_clock()
77 	*rate = SOC_ATMEL_SAM_UPLLCK_FREQ_HZ / (sam_cfg->divider);  in can_sam_get_core_clock()
84 	REG_PMC_PCK5 = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(sam_cfg->divider - 1);  in can_sam_clock_enable()
85 	PMC->PMC_SCER |= PMC_SCER_PCK5;  in can_sam_clock_enable()
89 			       (clock_control_subsys_t)&sam_cfg->clock_cfg);  in can_sam_clock_enable()
94 	const struct can_mcan_config *mcan_cfg = dev->config;  in can_sam_init()
95 	const struct can_sam_config *sam_cfg = mcan_cfg->custom;  in can_sam_init()
100 	ret = pinctrl_apply_state(sam_cfg->pcfg, PINCTRL_STATE_DEFAULT);  in can_sam_init()
106 	uint32_t mrba = sam_cfg->mram & 0xFFFF0000;  in can_sam_init()
109 	sys_write32((sys_read32(sam_cfg->dma_base) & 0x0000FFFF) | mrba, sam_cfg->dma_base);  in can_sam_init()
111 	ret = can_mcan_configure_mram(dev, mrba, sam_cfg->mram);  in can_sam_init()
121 	sam_cfg->config_irq();  in can_sam_init()
181 		.divider = DT_INST_PROP(inst, divider),			\