2  * Copyright (c) 2019-2021 Vestas Wind Systems A/S
5  * Copyright (c) 2014-2015 Wind River Systems, Inc.
8  * SPDX-License-Identifier: Apache-2.0
18 #define ASSERT_WITHIN_RANGE(val, min, max, str) \  argument
19 	BUILD_ASSERT(val >= min && val <= max, str)
21 #define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \  argument
22 	BUILD_ASSERT(val == 0 || val == 1 || val == 2 || val == 4 ||	\
23 		     val == 8 || val == 16 || val == 2 || val == 64, str)
25 #define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val)  argument
28 #define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)  argument
36 		    "Invalid SCG slow clock divider value");
38 		    "Invalid SCG bus clock divider value");
40 /* Core divider range is 1 to 4 with SPLL as clock source */
42 		    "Invalid SCG core clock divider value");
45 		    "Invalid SCG core clock divider value");
67 		       "Invalid SCG SOSC divider 1 value");
69 		       "Invalid SCG SOSC divider 2 value");
82 		       "Invalid SCG SIRC divider 1 value");
84 		       "Invalid SCG SIRC divider 2 value");
100 		       "Invalid SCG FIRC divider 1 value");
102 		       "Invalid SCG FIRC divider 2 value");
121 /* System Phase-Locked Loop (SPLL) configuration */
123 		    "Invalid SCG SPLL fixed divider value");
125 		       "Invalid SCG SPLL divider 1 value");
127 		       "Invalid SCG SPLL divider 2 value");
129 		    "Invalid SCG PLL pre divider value");
144 	.prediv      = (SCG_CLOCK_DIV(pll) - 1U),
145 	.mult        = (SCG_CLOCK_MULT(pll) - 16U)
250 	 * Note that the KE1xF does not implement the optional ARMv7-M memory  in soc_early_init_hook()
252 	 * Cortex-M4 core.  Instead, the processor includes its own MPU module.  in soc_early_init_hook()
254 	temp_reg = SYSMPU->CESR;  in soc_early_init_hook()
257 	SYSMPU->CESR = temp_reg;  in soc_early_init_hook()
288 	WDOG->CNT = WDOG_UPDATE_KEY;  in z_arm_watchdog_init()
289 	while (!(WDOG->CS & WDOG_CS_ULK_MASK)) {  in z_arm_watchdog_init()
297 	WDOG->TOVAL = CONFIG_WDOG_INITIAL_TIMEOUT >> 1;  in z_arm_watchdog_init()
298 	WDOG->CS = WDOG_CS_PRES(1) | WDOG_CS_CLK(1) | WDOG_CS_WAIT(1) |  in z_arm_watchdog_init()
301 	while (!(WDOG->CS & WDOG_CS_RCS_MASK)) {  in z_arm_watchdog_init()