Home
last modified time | relevance | path

Searched +full:cs +full:- +full:mode (Results 1 – 25 of 238) sorted by relevance

12345678910

/Zephyr-latest/include/zephyr/bluetooth/
Dcs.h8 * SPDX-License-Identifier: Apache-2.0
14 * @brief LE Channel Sounding (CS)
15 * @defgroup bt_le_cs Channel Sounding (CS)
31 * @brief Macro for getting a specific channel bit in CS channel map
41 * @brief Macro for setting a specific channel bit value in CS channel map
65 /** Default CS settings in the local Controller */
67 /** Enable CS initiator role. */
69 /** Enable CS reflector role. */
75 * for all CS transmissions.
83 /** CS Test CS_SYNC Antenna Identifier */
[all …]
/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
52 read-cs-idle-min-ns:
56 Min. time, in nanoseconds, the #CS line should remain inactive between
[all …]
/Zephyr-latest/dts/bindings/spi/
Despressif,esp32-spi.yaml3 compatible: "espressif,esp32-spi"
5 include: [spi-controller.yaml, pinctrl-device.yaml]
11 pinctrl-0:
14 pinctrl-names:
17 half-duplex:
20 Enable half-duplex communication mode.
24 dummy-comp:
31 Enable 3-wire mode
35 dma-enabled:
39 dma-clk:
[all …]
Dnxp,s32-spi.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,s32-spi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 num-cs:
26 pinctrl-0:
29 pinctrl-names:
35 Select if the SPI module is intended to be used in slave mode.
37 spi-sck-cs-delay:
41 deactivating Chip Select at the stop of transfer. If CS remains
[all …]
Dintel,penwell-spi.yaml3 # SPDX-License-Identifier: Apache-2.0
7 compatible: "intel,penwell-spi"
9 include: [spi-controller.yaml, pcie-device.yaml]
15 cs-gpios:
18 pw,cs-mode:
27 pw,cs-output:
37 pw,fifo-depth:
/Zephyr-latest/dts/bindings/mipi-dbi/
Dnxp,mipi-dbi-flexio-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,mipi-dbi-flexio-lcdif"
8 include: [mipi-dbi-controller.yaml, base.yaml, pinctrl-device.yaml]
11 shifters-count:
17 timers-count:
23 enwr-pin:
27 Pin select for WR(8080 mode), EN(6800 mode).
29 rd-pin:
32 Pin select for RD(8080 mode), not used in 6800 mode.
34 data-pin-start:
[all …]
Dzephyr,mipi-dbi-bitbang.yaml3 # SPDX-License-Identifier: Apache-2.0
6 MIPI-DBI Mode A and B bit banging controller. This driver emulates MIPI DBI mode A and B (6800
9 compatible: "zephyr,mipi-dbi-bitbang"
11 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
15 dc-gpios:
16 type: phandle-array
21 reset-gpios:
22 type: phandle-array
27 rd-gpios:
28 type: phandle-array
[all …]
Dmipi-dbi-spi-device.yaml2 # SPDX-License-Identifier: Apache-2.0
4 # Common fields for MIPI DBI devices using Mode C (SPI)
6 include: [mipi-dbi-device.yaml]
13 SPI Duplex mode, full or half. By default it's always full duplex thus 0
14 as this is, by far, the most common mode.
18 list (see dt-bindings/spi/spi.h)
21 mipi-cpol:
26 mipi-cpha:
31 mipi-hold-cs:
/Zephyr-latest/soc/espressif/common/
DKconfig.spiram2 # SPDX-License-Identifier: Apache-2.0
7 bool "Support for external, SPI-connected RAM"
40 prompt "Mode (QUAD/OCT) of SPI RAM chip in use"
44 bool "Quad Mode PSRAM"
47 bool "Octal Mode PSRAM"
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
66 bool "ESP-PSRAM64, LY68L6400 or APS6408"
134 bool "Move Read-Only Data in Flash to PSRAM"
148 Enable MSPI Error-Correcting Code function when accessing SPIRAM.
[all …]
/Zephyr-latest/drivers/spi/
Dspi_b91.c4 * SPDX-License-Identifier: Apache-2.0
38 #define SPI_CFG(dev) ((struct spi_b91_cfg *) ((dev)->config))
44 #define SPI_DATA(dev) ((struct spi_b91_data *) ((dev)->data))
47 /* disable hardware cs flow control */
52 /* loop through all cs pins (cs0..cs2) */ in spi_b91_hw_cs_disable()
54 /* get CS pin defined in device tree */ in spi_b91_hw_cs_disable()
55 pin = config->cs_pin[i]; in spi_b91_hw_cs_disable()
57 /* if CS pin is defined in device tree */ in spi_b91_hw_cs_disable()
59 if (config->peripheral_id == PSPI_MODULE) { in spi_b91_hw_cs_disable()
60 /* disable CS pin for PSPI */ in spi_b91_hw_cs_disable()
[all …]
/Zephyr-latest/drivers/memc/
Dmemc_sam_smc.c4 * SPDX-License-Identifier: Apache-2.0
18 uint32_t cs; member
19 uint32_t mode; member
36 const struct memc_smc_config *cfg = dev->config; in memc_smc_init()
41 (clock_control_subsys_t)&cfg->clock_cfg); in memc_smc_init()
43 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in memc_smc_init()
48 for (size_t i = 0U; i < cfg->banks_len; i++) { in memc_smc_init()
49 if (cfg->banks[i].cs >= SMCCS_NUMBER_NUMBER) { in memc_smc_init()
50 return -EINVAL; in memc_smc_init()
53 bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs]; in memc_smc_init()
[all …]
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dintel_rpl_p_crb.overlay4 * SPDX-License-Identifier: Apache-2.0
10 pw,cs-mode = <0>;
11 pw,cs-output = <0>;
15 compatible = "test-spi-loopback-slow";
17 spi-max-frequency = <500000>;
21 compatible = "test-spi-loopback-fast";
23 spi-max-frequency = <16000000>;
Dintel_rpl_s_crb.overlay4 * SPDX-License-Identifier: Apache-2.0
10 pw,cs-mode = <0>;
11 pw,cs-output = <0>;
15 compatible = "test-spi-loopback-slow";
17 spi-max-frequency = <500000>;
20 compatible = "test-spi-loopback-fast";
22 spi-max-frequency = <16000000>;
/Zephyr-latest/drivers/espi/
Despi_saf_mchp_xec.c5 * SPDX-License-Identifier: Apache-2.0
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
44 * Delay before first Poll-1 command after suspend in 20 ns units
72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
81 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
82 if (cs == 0) { in mchp_saf_poll2_mask_wr()
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
85 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
[all …]
Despi_saf_mchp_xec_v2.c5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
106 if (cs == 0) { in mchp_saf_poll2_mask_wr()
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
[all …]
/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_psram.overlay4 * SPDX-License-Identifier: Apache-2.0
9 sram-ext = &memc;
17 /* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */
20 is-ram;
21 dev-size = <DT_SIZE_M(64)>;
22 dev-type = <0x5D>;
23 dev-id = <0x0D>;
24 dev-density = <0xE040>;
25 reset-delay-us = <50>;
26 read-cs-idle-min-ns = <18>;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk_mimxrt1052_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 pinctrl-0 = <&pinmux_flexspi1>;
22 pinctrl-names = "default";
23 ahb-bufferable;
24 ahb-cacheable;
25 sck-differential-clock;
[all …]
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk_mimxrt1062_hyperflash.dts4 * SPDX-License-Identifier: Apache-2.0
11 zephyr,flash-controller = &s26ks512s0;
13 zephyr,code-partition = &slot0_partition;
19 ahb-prefetch;
20 ahb-read-addr-opt;
21 ahb-bufferable;
22 ahb-cacheable;
23 sck-differential-clock;
24 combination-mode;
25 rx-clock-source = <3>;
[all …]
/Zephyr-latest/include/zephyr/arch/x86/
Dmsr.h3 * SPDX-License-Identifier: Apache-2.0
32 /* STAR 31:0 Unused in long mode
33 * 47:32 Kernel CS (SS = CS+8)
34 * 63:48 User CS (SS = CS+8)
54 * z_x86_msr_write() is shared between 32- and 64-bit implementations, but
/Zephyr-latest/include/zephyr/drivers/
Dspi.h4 * SPDX-License-Identifier: Apache-2.0
27 #include <zephyr/dt-bindings/spi/spi.h>
39 * @name SPI operational mode
42 #define SPI_OP_MODE_MASTER 0U /**< Master mode. */
43 #define SPI_OP_MODE_SLAVE BIT(0) /**< Slave mode. */
47 /** Get SPI operational mode. */
73 * Whatever data is transmitted is looped-back to the receiving buffer of
81 /** Get SPI polarity and phase mode bits. */
115 /** Requests - if possible - to keep CS asserted after the transaction */
124 /** Active high logic on CS. Usually, and by default, CS logic is active
[all …]
/Zephyr-latest/dts/bindings/qspi/
Dnxp,s32-qspi.yaml2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
32 Selects the read mode:
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
[all …]
/Zephyr-latest/include/zephyr/arch/x86/intel64/
Dthread.h3 * SPDX-License-Identifier: Apache-2.0
12 * GDT selectors - these must agree with the GDT layout in locore.S.
15 #define X86_KERNEL_CS_32 0x08 /* 32-bit kernel code */
16 #define X86_KERNEL_DS_32 0x10 /* 32-bit kernel data */
17 #define X86_KERNEL_CS 0x18 /* 64-bit kernel code */
18 #define X86_KERNEL_DS 0x20 /* 64-bit kernel data */
19 #define X86_USER_CS_32 0x28 /* 32-bit user data (unused) */
20 #define X86_USER_DS 0x30 /* 64-bit user mode data */
21 #define X86_USER_CS 0x38 /* 64-bit user mode code */
24 * descriptors for implementing user mode with syscall/sysret
[all …]
/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
22 * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
25 * CS polarity is normal (active low). Zephyr's SPI driver model currently
28 * The logical alternative would be to put the CS into GPIO mode, perform 3
29 * separate SPI transfers (inverting CS polarity as necessary) and then
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
57 * with the GPIO bitbang mode. It is used both in fpga_ice40_send_clocks()
[all …]
/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_bitbang.c6 * SPDX-License-Identifier: Apache-2.0
20 /* Compile in a data bus LUT for improved performance if at least one instance uses an 8-bit bus */
38 /* Chip-select GPIO */
39 const struct gpio_dt_spec cs; member
48 /* Data GPIO remap look-up table. Valid if mipi_dbi_bitbang_data.single_port is set */
73 if (data->single_port) { in mipi_dbi_bitbang_set_data_gpios()
74 gpio_port_set_masked(data->data_port, config->data_mask, config->data_lut[value]); in mipi_dbi_bitbang_set_data_gpios()
77 for (int i = 0; i < config->data_bus_width; i++) { in mipi_dbi_bitbang_set_data_gpios()
78 gpio_pin_set_dt(&config->data[i], (value & (1 << i)) != 0); in mipi_dbi_bitbang_set_data_gpios()
89 const struct mipi_dbi_bitbang_config *config = dev->config; in mipi_dbi_bitbang_write_helper()
[all …]
/Zephyr-latest/arch/x86/core/
Dfatal.c3 * SPDX-License-Identifier: Apache-2.0
22 * -device isa-debug-exit,iobase=0xf4,iosize=0x04 in arch_system_halt()
27 * It has been observed that if the emulator exits for a triple-fault in arch_system_halt()
41 return esf->rsp; in esf_get_sp()
43 return esf->esp; in esf_get_sp()
48 bool z_x86_check_stack_bounds(uintptr_t addr, size_t size, uint16_t cs) in z_x86_check_stack_bounds() argument
58 cpu_id = arch_curr_cpu()->id; in z_x86_check_stack_bounds()
66 } else if ((cs & 0x3U) == 0U && in z_x86_check_stack_bounds()
67 (arch_current_thread()->base.user_options & K_USER) != 0) { in z_x86_check_stack_bounds()
68 /* The low two bits of the CS register is the privilege in z_x86_check_stack_bounds()
[all …]

12345678910