1 /*
2 * Copyright (c) 2019 Intel Corporation
3 * Copyright (c) 2020 Microchip Technology Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_xec_espi_saf
9
10 #include <zephyr/kernel.h>
11 #include <soc.h>
12 #include <errno.h>
13 #include <zephyr/drivers/espi.h>
14 #include <zephyr/drivers/espi_saf.h>
15 #include <zephyr/logging/log.h>
16
17 #include "espi_utils.h"
18 LOG_MODULE_REGISTER(espi_saf, CONFIG_ESPI_LOG_LEVEL);
19
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
21 #define MAX_SAF_ECP_BUFFER_SIZE 64ul
22
23 /* 1 second maximum for flash operations */
24 #define MAX_SAF_FLASH_TIMEOUT 125000ul /* 1000ul */
25
26 /* 64 bytes @ 24MHz quad is approx. 6 us */
27 #define SAF_WAIT_INTERVAL 8
28
29 /* After 8 wait intervals yield */
30 #define SAF_YIELD_THRESHOLD 64
31
32 struct espi_isr {
33 uint32_t girq_bit;
34 void (*the_isr)(const struct device *dev);
35 };
36
37 /*
38 * SAF configuration from Device Tree
39 * SAF controller register block base address
40 * QMSPI controller register block base address
41 * SAF communications register block base address
42 * Flash STATUS1 poll timeout in 32KHz periods
43 * Flash consecutive read timeout in units of 20 ns
44 * Delay before first Poll-1 command after suspend in 20 ns units
45 * Hold off suspend for this interval if erase or program in 32KHz periods.
46 * Add delay between Poll STATUS1 commands in 20 ns units.
47 */
48 struct espi_saf_xec_config {
49 uintptr_t saf_base_addr;
50 uintptr_t qmspi_base_addr;
51 uintptr_t saf_comm_base_addr;
52 uint32_t poll_timeout;
53 uint32_t consec_rd_timeout;
54 uint32_t sus_chk_delay;
55 uint16_t sus_rsm_interval;
56 uint16_t poll_interval;
57 };
58
59 struct espi_saf_xec_data {
60 sys_slist_t callbacks;
61 struct k_sem ecp_lock;
62 uint32_t hwstatus;
63 };
64
65 /* EC portal local flash r/w buffer */
66 static uint32_t slave_mem[MAX_SAF_ECP_BUFFER_SIZE];
67
68 /*
69 * @brief eSPI SAF configuration
70 */
71
mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS * regs,uint8_t cs,uint32_t val)72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
73 uint32_t val)
74 {
75 regs->SAF_CS_OP[cs].OP_DESCR = val;
76 }
77
mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS * regs,uint8_t cs,uint16_t val)78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
79 uint16_t val)
80 {
81 LOG_DBG("%s cs: %d mask %x", __func__, cs, val);
82 if (cs == 0) {
83 regs->SAF_CS0_CFG_P2M = val;
84 } else {
85 regs->SAF_CS1_CFG_P2M = val;
86 }
87 }
88
mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS * regs,uint8_t cs,uint16_t val)89 static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs,
90 uint16_t val)
91 {
92 if (cs == 0) {
93 regs->SAF_CS0_CM_PRF = val;
94 } else {
95 regs->SAF_CS1_CM_PRF = val;
96 }
97 }
98
99 /* busy wait or yield until we have SAF interrupt support */
xec_saf_spin_yield(int * counter)100 static int xec_saf_spin_yield(int *counter)
101 {
102 *counter = *counter + 1;
103
104 if (*counter > MAX_SAF_FLASH_TIMEOUT) {
105 return -ETIMEDOUT;
106 }
107
108 if (*counter > SAF_YIELD_THRESHOLD) {
109 k_yield();
110 } else {
111 k_busy_wait(SAF_WAIT_INTERVAL);
112 }
113
114 return 0;
115 }
116
117 /*
118 * Initialize SAF flash protection regions.
119 * SAF HW implements 17 protection regions.
120 * At least one protection region must be configured to allow
121 * EC access to the local flash through the EC Portal.
122 * Each protection region is composed of 4 32-bit registers
123 * Start bits[19:0] = bits[31:12] region start address (4KB boundaries)
124 * Limit bits[19:0] = bits[31:12] region limit address (4KB boundaries)
125 * Write protect b[7:0] = masters[7:0] allow write/erase. 1=allowed
126 * Read protetc b[7:0] = masters[7:0] allow read. 1=allowed
127 *
128 * This routine configures protection region 0 for full flash array
129 * address range and read-write-erase for all masters.
130 * This routine must be called AFTER the flash configuration size/limit and
131 * threshold registers have been programmed.
132 *
133 * POR default values:
134 * Start = 0x7ffff
135 * Limit = 0
136 * Write Prot = 0x01 Master 0 always granted write/erase
137 * Read Prot = 0x01 Master 0 always granted read
138 *
139 * Sample code configures PR[0]
140 * Start = 0
141 * Limit = 0x7ffff
142 * WR = 0xFF
143 * RD = 0xFF
144 */
saf_protection_regions_init(MCHP_SAF_HW_REGS * regs)145 static void saf_protection_regions_init(MCHP_SAF_HW_REGS *regs)
146 {
147 LOG_DBG("%s", __func__);
148
149 for (size_t n = 0; n < MCHP_ESPI_SAF_PR_MAX; n++) {
150 if (n == 0) {
151 regs->SAF_PROT_RG[0].START = 0U;
152 regs->SAF_PROT_RG[0].LIMIT =
153 regs->SAF_FL_CFG_SIZE_LIM >> 12;
154 regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL;
155 regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL;
156 } else {
157 regs->SAF_PROT_RG[n].START =
158 MCHP_SAF_PROT_RG_START_DFLT;
159 regs->SAF_PROT_RG[n].LIMIT =
160 MCHP_SAF_PROT_RG_LIMIT_DFLT;
161 regs->SAF_PROT_RG[n].WEBM = 0U;
162 regs->SAF_PROT_RG[n].RDBM = 0U;
163 }
164
165 LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START);
166 LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT);
167 LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM);
168 LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM);
169 }
170 }
171
qmspi_freq_div(uint32_t freqhz)172 static uint32_t qmspi_freq_div(uint32_t freqhz)
173 {
174 uint32_t fdiv;
175
176 if (freqhz < (MCHP_QMSPI_MIN_FREQ_KHZ * 1000U)) {
177 fdiv = 0U; /* freq divider field -> 256 */
178 } else if (freqhz >= (MCHP_QMSPI_MAX_FREQ_KHZ * 1000U)) {
179 fdiv = 1U;
180 } else {
181 /* truncation produces next higher integer frequency */
182 fdiv = MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ / freqhz;
183 }
184
185 fdiv &= MCHP_QMSPI_M_FDIV_MASK0;
186 fdiv <<= MCHP_QMSPI_M_FDIV_POS;
187
188 return fdiv;
189 }
190
191 /*
192 * Take over and re-initialize QMSPI for use by SAF HW engine.
193 * When SAF is activated, QMSPI registers are controlled by SAF
194 * HW engine. CPU no longer has access to QMSPI registers.
195 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
196 * chip select timing.
197 * 2. Put QMSPI controller in a known state by performing a soft reset.
198 * 3. Clear QMSPI GIRQ status
199 * 4. Configure QMSPI interface control for SAF.
200 * 5. Load flash device independent (generic) descriptors.
201 * 6. Enable transfer done interrupt in QMSPI
202 * 7. Enable QMSPI SAF mode
203 * 8. If user configuration overrides frequency, signalling mode,
204 * or chip select timing derive user values.
205 * 9. Program QMSPI MODE and CSTIM registers with activate set.
206 */
saf_qmspi_init(const struct espi_saf_xec_config * xcfg,const struct espi_saf_cfg * cfg)207 static int saf_qmspi_init(const struct espi_saf_xec_config *xcfg,
208 const struct espi_saf_cfg *cfg)
209 {
210 uint32_t qmode, cstim, n;
211 QMSPI_Type *regs = (QMSPI_Type *)xcfg->qmspi_base_addr;
212 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
213
214 qmode = regs->MODE;
215 if (!(qmode & MCHP_QMSPI_M_ACTIVATE)) {
216 return -EAGAIN;
217 }
218
219 qmode = regs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK);
220 cstim = regs->CSTM;
221 regs->MODE = MCHP_QMSPI_M_SRST;
222 regs->STS = MCHP_QMSPI_STS_RW1C_MASK;
223
224 MCHP_GIRQ_ENCLR(MCHP_QMSPI_GIRQ_NUM) = MCHP_QMSPI_GIRQ_VAL;
225 MCHP_GIRQ_SRC(MCHP_QMSPI_GIRQ_NUM) = MCHP_QMSPI_GIRQ_VAL;
226
227 regs->IFCTRL =
228 (MCHP_QMSPI_IFC_WP_OUT_HI | MCHP_QMSPI_IFC_WP_OUT_EN |
229 MCHP_QMSPI_IFC_HOLD_OUT_HI | MCHP_QMSPI_IFC_HOLD_OUT_EN);
230
231 for (n = 0; n < MCHP_SAF_NUM_GENERIC_DESCR; n++) {
232 regs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] =
233 hwcfg->generic_descr[n];
234 }
235
236 regs->IEN = MCHP_QMSPI_IEN_XFR_DONE;
237
238 qmode |= (MCHP_QMSPI_M_SAF_DMA_MODE_EN | MCHP_QMSPI_M_CS0 |
239 MCHP_QMSPI_M_ACTIVATE);
240
241 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CPHA) {
242 qmode = (qmode & ~(MCHP_QMSPI_M_SIG_MASK)) |
243 ((hwcfg->qmspi_cpha << MCHP_QMSPI_M_SIG_POS) &
244 MCHP_QMSPI_M_SIG_MASK);
245 }
246
247 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_FREQ) {
248 qmode = (qmode & ~(MCHP_QMSPI_M_FDIV_MASK)) |
249 qmspi_freq_div(hwcfg->qmspi_freq_hz);
250 }
251
252 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CSTM) {
253 cstim = hwcfg->qmspi_cs_timing;
254 }
255
256 regs->MODE = qmode;
257 regs->CSTM = cstim;
258
259 return 0;
260 }
261
262 /*
263 * Registers at offsets:
264 * SAF Poll timeout @ 0x194. Hard coded to 0x28000. Default value = 0.
265 * recommended value = 0x28000 32KHz clocks (5 seconds). b[17:0]
266 * SAF Poll interval @ 0x198. Hard coded to 0
267 * Default value = 0. Recommended = 0. b[15:0]
268 * SAF Suspend/Resume Interval @ 0x19c. Hard coded to 0x8
269 * Default value = 0x01. Min time erase/prog in 32KHz units.
270 * SAF Consecutive Read Timeout @ 0x1a0. Hard coded to 0x2. b[15:0]
271 * Units of MCLK. Recommend < 20us. b[19:0]
272 * SAF Suspend Check Delay @ 0x1ac. Not touched.
273 * Default = 0. Recommend = 20us. Units = MCLK. b[19:0]
274 */
saf_flash_timing_init(MCHP_SAF_HW_REGS * regs,const struct espi_saf_xec_config * cfg)275 static void saf_flash_timing_init(MCHP_SAF_HW_REGS *regs,
276 const struct espi_saf_xec_config *cfg)
277 {
278 LOG_DBG("%s\n", __func__);
279 regs->SAF_POLL_TMOUT = cfg->poll_timeout;
280 regs->SAF_POLL_INTRVL = cfg->poll_interval;
281 regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval;
282 regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout;
283 regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay;
284 LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT);
285 LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL);
286 LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL);
287 LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT);
288 LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY);
289 }
290
291 /*
292 * Disable DnX bypass feature.
293 */
saf_dnx_bypass_init(MCHP_SAF_HW_REGS * regs)294 static void saf_dnx_bypass_init(MCHP_SAF_HW_REGS *regs)
295 {
296 regs->SAF_DNX_PROT_BYP = 0;
297 regs->SAF_DNX_PROT_BYP = 0xffffffff;
298 }
299
300 /*
301 * Bitmap of flash erase size from 1KB up to 128KB.
302 * eSPI SAF specification requires 4KB erase support.
303 * MCHP SAF supports 4KB, 32KB, and 64KB.
304 * Only report 32KB and 64KB to Host if supported by both
305 * flash devices.
306 */
saf_init_erase_block_size(const struct espi_saf_cfg * cfg)307 static int saf_init_erase_block_size(const struct espi_saf_cfg *cfg)
308 {
309 struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
310 uint32_t opb = fcfg->opb;
311 uint8_t erase_bitmap = MCHP_ESPI_SERASE_SZ_4K;
312
313 LOG_DBG("%s\n", __func__);
314
315 if (cfg->nflash_devices > 1) {
316 fcfg++;
317 opb &= fcfg->opb;
318 }
319
320 if ((opb & MCHP_SAF_CS_OPB_ER0_MASK) == 0) {
321 /* One or both do not support 4KB erase! */
322 return -EINVAL;
323 }
324
325 if (opb & MCHP_SAF_CS_OPB_ER1_MASK) {
326 erase_bitmap |= MCHP_ESPI_SERASE_SZ_32K;
327 }
328
329 if (opb & MCHP_SAF_CS_OPB_ER2_MASK) {
330 erase_bitmap |= MCHP_ESPI_SERASE_SZ_64K;
331 }
332
333 ESPI_CAP_REGS->FC_SERBZ = erase_bitmap;
334
335 return 0;
336 }
337
338 /*
339 * Set the continuous mode prefix and 4-byte address mode bits
340 * based upon the flash configuration information.
341 * Updates:
342 * SAF Flash Config Poll2 Mask @ 0x1A4
343 * SAF Flash Config Special Mode @ 0x1B0
344 * SAF Flash Misc Config @ 0x38
345 */
saf_flash_misc_cfg(MCHP_SAF_HW_REGS * regs,uint8_t cs,const struct espi_saf_flash_cfg * fcfg)346 static void saf_flash_misc_cfg(MCHP_SAF_HW_REGS *regs, uint8_t cs,
347 const struct espi_saf_flash_cfg *fcfg)
348 {
349 uint32_t d, v;
350
351 d = regs->SAF_FL_CFG_MISC;
352
353 v = MCHP_SAF_FL_CFG_MISC_CS0_CPE;
354 if (cs) {
355 v = MCHP_SAF_FL_CFG_MISC_CS1_CPE;
356 }
357
358 /* Does this flash device require a prefix for continuous mode? */
359 if (fcfg->cont_prefix != 0) {
360 d |= v;
361 } else {
362 d &= ~v;
363 }
364
365 v = MCHP_SAF_FL_CFG_MISC_CS0_4BM;
366 if (cs) {
367 v = MCHP_SAF_FL_CFG_MISC_CS1_4BM;
368 }
369
370 /* Use 32-bit addressing for this flash device? */
371 if (fcfg->flags & MCHP_FLASH_FLAG_ADDR32) {
372 d |= v;
373 } else {
374 d &= ~v;
375 }
376
377 regs->SAF_FL_CFG_MISC = d;
378 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, d);
379 }
380
381 /*
382 * Program flash device specific SAF and QMSPI registers.
383 *
384 * CS0 OpA @ 0x4c or CS1 OpA @ 0x5C
385 * CS0 OpB @ 0x50 or CS1 OpB @ 0x60
386 * CS0 OpC @ 0x54 or CS1 OpC @ 0x64
387 * Poll 2 Mask @ 0x1a4
388 * Continuous Prefix @ 0x1b0
389 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
390 * CS0 Descrs @ 0x58 or CS1 Descrs @ 0x68
391 */
saf_flash_cfg(const struct device * dev,const struct espi_saf_flash_cfg * fcfg,uint8_t cs)392 static void saf_flash_cfg(const struct device *dev,
393 const struct espi_saf_flash_cfg *fcfg, uint8_t cs)
394 {
395 uint32_t d, did;
396 const struct espi_saf_xec_config *xcfg = dev->config;
397 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
398 QMSPI_Type *qregs = (QMSPI_Type *)xcfg->qmspi_base_addr;
399
400 LOG_DBG("%s cs=%u", __func__, cs);
401
402 regs->SAF_CS_OP[cs].OPA = fcfg->opa;
403 regs->SAF_CS_OP[cs].OPB = fcfg->opb;
404 regs->SAF_CS_OP[cs].OPC = fcfg->opc;
405 regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids;
406
407 did = MCHP_SAF_QMSPI_CS0_START_DESCR;
408 if (cs != 0) {
409 did = MCHP_SAF_QMSPI_CS1_START_DESCR;
410 }
411
412 for (size_t i = 0; i < MCHP_SAF_QMSPI_NUM_FLASH_DESCR; i++) {
413 d = fcfg->descr[i] & ~(MCHP_QMSPI_C_NEXT_DESCR_MASK);
414 d |= (((did + 1) << MCHP_QMSPI_C_NEXT_DESCR_POS) &
415 MCHP_QMSPI_C_NEXT_DESCR_MASK);
416 qregs->DESCR[did++] = d;
417 }
418
419 mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask);
420 mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix);
421 saf_flash_misc_cfg(regs, cs, fcfg);
422 }
423
424 static const uint32_t tag_map_dflt[MCHP_ESPI_SAF_TAGMAP_MAX] = {
425 MCHP_SAF_TAG_MAP0_DFLT, MCHP_SAF_TAG_MAP1_DFLT, MCHP_SAF_TAG_MAP2_DFLT
426 };
427
saf_tagmap_init(MCHP_SAF_HW_REGS * regs,const struct espi_saf_cfg * cfg)428 static void saf_tagmap_init(MCHP_SAF_HW_REGS *regs,
429 const struct espi_saf_cfg *cfg)
430 {
431 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg;
432
433 for (int i = 0; i < MCHP_ESPI_SAF_TAGMAP_MAX; i++) {
434 if (hwcfg->tag_map[i] & MCHP_SAF_HW_CFG_TAGMAP_USE) {
435 regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i];
436 } else {
437 regs->SAF_TAG_MAP[i] = tag_map_dflt[i];
438 }
439 }
440
441 LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]);
442 LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]);
443 LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]);
444 }
445
446 /*
447 * Configure SAF and QMSPI for SAF operation based upon the
448 * number and characteristics of local SPI flash devices.
449 * NOTE: SAF is configured but not activated. SAF should be
450 * activated only when eSPI master sends Flash Channel enable
451 * message with MAF/SAF select flag.
452 */
espi_saf_xec_configuration(const struct device * dev,const struct espi_saf_cfg * cfg)453 static int espi_saf_xec_configuration(const struct device *dev,
454 const struct espi_saf_cfg *cfg)
455 {
456 int ret = 0;
457 uint32_t totalsz = 0;
458 uint32_t u = 0;
459
460 LOG_DBG("%s", __func__);
461
462 if ((dev == NULL) || (cfg == NULL)) {
463 return -EINVAL;
464 }
465
466 const struct espi_saf_xec_config *xcfg = dev->config;
467 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
468 const struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs;
469
470 if ((fcfg == NULL) || (cfg->nflash_devices == 0U) ||
471 (cfg->nflash_devices > MCHP_SAF_MAX_FLASH_DEVICES)) {
472 return -EINVAL;
473 }
474
475 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
476 return -EAGAIN;
477 }
478
479 saf_qmspi_init(xcfg, cfg);
480
481 regs->SAF_CS0_CFG_P2M = 0;
482 regs->SAF_CS1_CFG_P2M = 0;
483
484 regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD;
485
486 /* flash device connected to CS0 required */
487 totalsz = fcfg->flashsz;
488 regs->SAF_FL_CFG_THRH = totalsz;
489 saf_flash_cfg(dev, fcfg, 0);
490
491 /* optional second flash device connected to CS1 */
492 if (cfg->nflash_devices > 1) {
493 fcfg++;
494 totalsz += fcfg->flashsz;
495 }
496 /* Program CS1 configuration (same as CS0 if only one device) */
497 saf_flash_cfg(dev, fcfg, 1);
498
499 if (totalsz == 0) {
500 return -EAGAIN;
501 }
502
503 regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1;
504
505 LOG_DBG("SAF_FL_CFG_THRH = %x SAF_FL_CFG_SIZE_LIM = %x",
506 regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM);
507
508 saf_tagmap_init(regs, cfg);
509
510 saf_protection_regions_init(regs);
511
512 saf_dnx_bypass_init(regs);
513
514 saf_flash_timing_init(regs, xcfg);
515
516 ret = saf_init_erase_block_size(cfg);
517 if (ret != 0) {
518 LOG_ERR("SAF Config bad flash erase config");
519 return ret;
520 }
521
522 /* Default or expedited prefetch? */
523 u = MCHP_SAF_FL_CFG_MISC_PFOE_DFLT;
524 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEXP) {
525 u = MCHP_SAF_FL_CFG_MISC_PFOE_EXP;
526 }
527
528 regs->SAF_FL_CFG_MISC =
529 (regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u;
530
531 /* enable prefetch ? */
532 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEN) {
533 MCHP_SAF_COMM_MODE_REG |= MCHP_SAF_COMM_MODE_PF_EN;
534 } else {
535 MCHP_SAF_COMM_MODE_REG &= ~(MCHP_SAF_COMM_MODE_PF_EN);
536 }
537
538 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC);
539 LOG_DBG("%s Aft MCHP_SAF_COMM_MODE_REG: %x", __func__,
540 MCHP_SAF_COMM_MODE_REG);
541
542 return 0;
543 }
544
espi_saf_xec_set_pr(const struct device * dev,const struct espi_saf_protection * pr)545 static int espi_saf_xec_set_pr(const struct device *dev,
546 const struct espi_saf_protection *pr)
547 {
548 if ((dev == NULL) || (pr == NULL)) {
549 return -EINVAL;
550 }
551
552 if (pr->nregions >= MCHP_ESPI_SAF_PR_MAX) {
553 return -EINVAL;
554 }
555
556 const struct espi_saf_xec_config *xcfg = dev->config;
557 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr;
558
559 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
560 return -EAGAIN;
561 }
562
563 const struct espi_saf_pr *preg = pr->pregions;
564 size_t n = pr->nregions;
565
566 while (n--) {
567 uint8_t regnum = preg->pr_num;
568
569 if (regnum >= MCHP_ESPI_SAF_PR_MAX) {
570 return -EINVAL;
571 }
572
573 /* NOTE: If previously locked writes have no effect */
574 if (preg->flags & MCHP_SAF_PR_FLAG_ENABLE) {
575 regs->SAF_PROT_RG[regnum].START = preg->start >> 12U;
576 regs->SAF_PROT_RG[regnum].LIMIT =
577 (preg->start + preg->size - 1U) >> 12U;
578 regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we;
579 regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd;
580 } else {
581 regs->SAF_PROT_RG[regnum].START = 0x7FFFFU;
582 regs->SAF_PROT_RG[regnum].LIMIT = 0U;
583 regs->SAF_PROT_RG[regnum].WEBM = 0U;
584 regs->SAF_PROT_RG[regnum].RDBM = 0U;
585 }
586
587 if (preg->flags & MCHP_SAF_PR_FLAG_LOCK) {
588 regs->SAF_PROT_LOCK |= (1UL << regnum);
589 }
590
591 preg++;
592 }
593
594 return 0;
595 }
596
espi_saf_xec_channel_ready(const struct device * dev)597 static bool espi_saf_xec_channel_ready(const struct device *dev)
598 {
599 const struct espi_saf_xec_config *cfg = dev->config;
600 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
601
602 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) {
603 return true;
604 }
605
606 return false;
607 }
608
609 /*
610 * MCHP SAF hardware supports a range of flash block erase
611 * sizes from 1KB to 128KB. The eSPI Host specification requires
612 * 4KB must be supported. The MCHP SAF QMSPI HW interface only
613 * supported three erase sizes. Most SPI flash devices chosen for
614 * SAF support 4KB, 32KB, and 64KB.
615 * Get flash erase sizes driver has configured from eSPI capabilities
616 * registers. We assume driver flash tables have opcodes to match
617 * capabilities configuration.
618 * Check requested erase size is supported.
619 */
620 struct erase_size_encoding {
621 uint8_t hwbitpos;
622 uint8_t encoding;
623 };
624
625 static const struct erase_size_encoding ersz_enc[] = {
626 { MCHP_ESPI_SERASE_SZ_4K_BITPOS, 0 },
627 { MCHP_ESPI_SERASE_SZ_32K_BITPOS, 1 },
628 { MCHP_ESPI_SERASE_SZ_64K_BITPOS, 2 }
629 };
630
631 #define SAF_ERASE_ENCODING_MAX_ENTRY \
632 (sizeof(ersz_enc) / sizeof(struct erase_size_encoding))
633
get_erase_size_encoding(uint32_t erase_size)634 static uint32_t get_erase_size_encoding(uint32_t erase_size)
635 {
636 uint8_t supsz = ESPI_CAP_REGS->FC_SERBZ;
637
638 LOG_DBG("%s\n", __func__);
639 for (int i = 0; i < SAF_ERASE_ENCODING_MAX_ENTRY; i++) {
640 uint32_t sz = MCHP_ESPI_SERASE_SZ(ersz_enc[i].hwbitpos);
641
642 if ((sz == erase_size) &&
643 (supsz & (1 << ersz_enc[i].hwbitpos))) {
644 return ersz_enc[i].encoding;
645 }
646 }
647
648 return 0xffffffffU;
649 }
650
check_ecp_access_size(uint32_t reqlen)651 static int check_ecp_access_size(uint32_t reqlen)
652 {
653 if ((reqlen < MCHP_SAF_ECP_CMD_RW_LEN_MIN) ||
654 (reqlen > MCHP_SAF_ECP_CMD_RW_LEN_MAX)) {
655 return -EAGAIN;
656 }
657
658 return 0;
659 }
660
661 /*
662 * EC access (read/erase/write) to SAF attached flash array
663 * cmd 0 = read
664 * 1 = write
665 * 2 = erase
666 */
saf_ecp_access(const struct device * dev,struct espi_saf_packet * pckt,uint8_t cmd)667 static int saf_ecp_access(const struct device *dev,
668 struct espi_saf_packet *pckt, uint8_t cmd)
669 {
670 uint32_t err_mask, n;
671 int rc, counter;
672 struct espi_saf_xec_data *xdat = dev->data;
673 const struct espi_saf_xec_config *cfg = dev->config;
674 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
675
676 counter = 0;
677 err_mask = MCHP_SAF_ECP_STS_ERR_MASK;
678
679 LOG_DBG("%s", __func__);
680
681 if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) {
682 LOG_ERR("SAF is disabled");
683 return -EIO;
684 }
685
686 if (regs->SAF_ECP_BUSY & MCHP_SAF_ECP_BUSY) {
687 LOG_ERR("SAF EC Portal is busy");
688 return -EBUSY;
689 }
690
691 if ((cmd == MCHP_SAF_ECP_CMD_CTYPE_READ0) ||
692 (cmd == MCHP_SAF_ECP_CMD_CTYPE_WRITE0)) {
693 rc = check_ecp_access_size(pckt->len);
694 if (rc) {
695 LOG_ERR("SAF EC Portal size out of bounds");
696 return rc;
697 }
698
699 if (cmd == MCHP_SAF_ECP_CMD_CTYPE_WRITE0) {
700 memcpy(slave_mem, pckt->buf, pckt->len);
701 }
702
703 n = pckt->len;
704 } else if (cmd == MCHP_SAF_ECP_CMD_CTYPE_ERASE0) {
705 n = get_erase_size_encoding(pckt->len);
706 if (n == 0xffffffff) {
707 LOG_ERR("SAF EC Portal unsupported erase size");
708 return -EAGAIN;
709 }
710 } else {
711 LOG_ERR("SAF EC Portal bad cmd");
712 return -EAGAIN;
713 }
714
715 LOG_DBG("%s params val done", __func__);
716
717 k_sem_take(&xdat->ecp_lock, K_FOREVER);
718
719 regs->SAF_ECP_INTEN = 0;
720 regs->SAF_ECP_STATUS = 0xffffffff;
721
722 /*
723 * TODO - Force SAF Done interrupt disabled until we have support
724 * from eSPI driver.
725 */
726 MCHP_GIRQ_ENCLR(MCHP_SAF_GIRQ) = MCHP_SAF_GIRQ_ECP_DONE_BIT;
727 MCHP_GIRQ_SRC(MCHP_SAF_GIRQ) = MCHP_SAF_GIRQ_ECP_DONE_BIT;
728
729 regs->SAF_ECP_FLAR = pckt->flash_addr;
730 regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0];
731
732 regs->SAF_ECP_CMD =
733 MCHP_SAF_ECP_CMD_PUT_FLASH_NP |
734 ((uint32_t)cmd << MCHP_SAF_ECP_CMD_CTYPE_POS) |
735 ((n << MCHP_SAF_ECP_CMD_LEN_POS) & MCHP_SAF_ECP_CMD_LEN_MASK);
736
737 /* TODO when interrupts are available enable here */
738 regs->SAF_ECP_START = MCHP_SAF_ECP_START;
739
740 /* TODO
741 * ISR is in eSPI driver. Use polling until eSPI driver has been
742 * modified to provide callback for GIRQ19 SAF ECP Done.
743 */
744 rc = 0;
745 xdat->hwstatus = regs->SAF_ECP_STATUS;
746 while (!(xdat->hwstatus & MCHP_SAF_ECP_STS_DONE)) {
747 rc = xec_saf_spin_yield(&counter);
748 if (rc < 0) {
749 goto ecp_exit;
750 }
751 xdat->hwstatus = regs->SAF_ECP_STATUS;
752 }
753
754 /* clear hardware status and check for errors */
755 regs->SAF_ECP_STATUS = xdat->hwstatus;
756 if (xdat->hwstatus & MCHP_SAF_ECP_STS_ERR_MASK) {
757 rc = -EIO;
758 goto ecp_exit;
759 }
760
761 if (cmd == MCHP_SAF_ECP_CMD_CTYPE_READ0) {
762 memcpy(pckt->buf, slave_mem, pckt->len);
763 }
764
765 ecp_exit:
766 k_sem_give(&xdat->ecp_lock);
767
768 return rc;
769 }
770
771 /* Flash read using SAF EC Portal */
saf_xec_flash_read(const struct device * dev,struct espi_saf_packet * pckt)772 static int saf_xec_flash_read(const struct device *dev,
773 struct espi_saf_packet *pckt)
774 {
775 LOG_DBG("%s", __func__);
776 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_READ0);
777 }
778
779 /* Flash write using SAF EC Portal */
saf_xec_flash_write(const struct device * dev,struct espi_saf_packet * pckt)780 static int saf_xec_flash_write(const struct device *dev,
781 struct espi_saf_packet *pckt)
782 {
783 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_WRITE0);
784 }
785
786 /* Flash erase using SAF EC Portal */
saf_xec_flash_erase(const struct device * dev,struct espi_saf_packet * pckt)787 static int saf_xec_flash_erase(const struct device *dev,
788 struct espi_saf_packet *pckt)
789 {
790 return saf_ecp_access(dev, pckt, MCHP_SAF_ECP_CMD_CTYPE_ERASE0);
791 }
792
espi_saf_xec_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)793 static int espi_saf_xec_manage_callback(const struct device *dev,
794 struct espi_callback *callback,
795 bool set)
796 {
797 struct espi_saf_xec_data *data = dev->data;
798
799 return espi_manage_callback(&data->callbacks, callback, set);
800 }
801
espi_saf_xec_activate(const struct device * dev)802 static int espi_saf_xec_activate(const struct device *dev)
803 {
804 const struct espi_saf_xec_config *cfg;
805 MCHP_SAF_HW_REGS *regs;
806
807 if (dev == NULL) {
808 return -EINVAL;
809 }
810
811 cfg = dev->config;
812 regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr;
813
814 regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN;
815
816 return 0;
817 }
818
819 static int espi_saf_xec_init(const struct device *dev);
820
821 static DEVICE_API(espi_saf, espi_saf_xec_driver_api) = {
822 .config = espi_saf_xec_configuration,
823 .set_protection_regions = espi_saf_xec_set_pr,
824 .activate = espi_saf_xec_activate,
825 .get_channel_status = espi_saf_xec_channel_ready,
826 .flash_read = saf_xec_flash_read,
827 .flash_write = saf_xec_flash_write,
828 .flash_erase = saf_xec_flash_erase,
829 .manage_callback = espi_saf_xec_manage_callback,
830 };
831
832 static struct espi_saf_xec_data espi_saf_xec_data;
833
834 static const struct espi_saf_xec_config espi_saf_xec_config = {
835 .saf_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 0),
836 .qmspi_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 1),
837 .saf_comm_base_addr = DT_INST_REG_ADDR_BY_IDX(0, 2),
838 .poll_timeout = DT_INST_PROP_OR(inst, poll_timeout,
839 MCHP_SAF_FLASH_POLL_TIMEOUT),
840 .consec_rd_timeout = DT_INST_PROP_OR(
841 inst, consec_rd_timeout, MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT),
842 .sus_chk_delay = DT_INST_PROP_OR(inst, sus_chk_delay,
843 MCHP_SAF_FLASH_SUS_CHK_DELAY),
844 .sus_rsm_interval = DT_INST_PROP_OR(inst, sus_rsm_interval,
845 MCHP_SAF_FLASH_SUS_RSM_INTERVAL),
846 .poll_interval = DT_INST_PROP_OR(inst, poll_interval,
847 MCHP_SAF_FLASH_POLL_INTERVAL),
848 };
849
850 DEVICE_DT_INST_DEFINE(0, &espi_saf_xec_init, NULL,
851 &espi_saf_xec_data, &espi_saf_xec_config, POST_KERNEL,
852 CONFIG_ESPI_TAF_INIT_PRIORITY, &espi_saf_xec_driver_api);
853
espi_saf_xec_init(const struct device * dev)854 static int espi_saf_xec_init(const struct device *dev)
855 {
856 struct espi_saf_xec_data *data = dev->data;
857
858 /* ungate SAF clocks by disabling PCR sleep enable */
859 mchp_pcr_periph_slp_ctrl(PCR_ESPI_SAF, MCHP_PCR_SLEEP_DIS);
860
861 /* reset the SAF block */
862 mchp_pcr_periph_reset(PCR_ESPI_SAF);
863
864 /* Configure the channels and its capabilities based on build config */
865 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP;
866 ESPI_CAP_REGS->FC_CAP &= ~(MCHP_ESPI_FC_CAP_SHARE_MASK);
867 ESPI_CAP_REGS->FC_CAP |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF;
868
869 k_sem_init(&data->ecp_lock, 1, 1);
870
871 return 0;
872 }
873
