5  * SPDX-License-Identifier: Apache-2.0
22  * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
25  * CS polarity is normal (active low). Zephyr's SPI driver model currently
28  * The logical alternative would be to put the CS into GPIO mode, perform 3
29  * separate SPI transfers (inverting CS polarity as necessary) and then
30  * restore the default pinctrl settings. On some higher-end microcontrollers
34  * However, on lower-end microcontrollers, the amount of time that elapses
36  * leaves us with the bitbanging option. Of course, on lower-end
40  * in order to bitbang on lower-end microcontrollers, we actually require
57  * with the GPIO bitbang mode. It is used both in fpga_ice40_send_clocks()
61  * lattice,ice40-fpga.yaml for details.
65 	for (; n > 0; --n) {  in fpga_ice40_delay()
73 	for (; n > 0; --n) {  in fpga_ice40_send_clocks()
82 				     volatile gpio_port_pins_t *clear, gpio_port_pins_t cs,  in fpga_ice40_spi_send_data()  argument
88 	/* assert chip-select (active low) */  in fpga_ice40_spi_send_data()
89 	*clear |= cs;  in fpga_ice40_spi_send_data()
91 	for (; n > 0; --n, ++z) {  in fpga_ice40_spi_send_data()
93 		for (int b = 7; b >= 0; --b) {  in fpga_ice40_spi_send_data()
112 	/* de-assert chip-select (active low) */  in fpga_ice40_spi_send_data()
113 	*set |= cs;  in fpga_ice40_spi_send_data()
118  * pp 15-21.
126 	gpio_port_pins_t cs;  in fpga_ice40_load()  local
131 	struct fpga_ice40_data *data = dev->data;  in fpga_ice40_load()
132 	const struct fpga_ice40_config *config = dev->config;  in fpga_ice40_load()
133 	const struct fpga_ice40_config_bitbang *config_bitbang = config->derived_config;  in fpga_ice40_load()
135 	if (!device_is_ready(config_bitbang->clk.port)) {  in fpga_ice40_load()
136 		LOG_ERR("%s: GPIO for clk is not ready", dev->name);  in fpga_ice40_load()
137 		return -ENODEV;  in fpga_ice40_load()
140 	if (!device_is_ready(config_bitbang->pico.port)) {  in fpga_ice40_load()
141 		LOG_ERR("%s: GPIO for pico is not ready", dev->name);  in fpga_ice40_load()
142 		return -ENODEV;  in fpga_ice40_load()
146 	cs = BIT(config->bus.config.cs.gpio.pin);  in fpga_ice40_load()
147 	clk = BIT(config_bitbang->clk.pin);  in fpga_ice40_load()
148 	pico = BIT(config_bitbang->pico.pin);  in fpga_ice40_load()
149 	creset = BIT(config->creset.pin);  in fpga_ice40_load()
153 	if (data->loaded && crc == data->crc) {  in fpga_ice40_load()
154 		LOG_WRN("already loaded with image CRC32c: 0x%08x", data->crc);  in fpga_ice40_load()
157 	key = k_spin_lock(&data->lock);  in fpga_ice40_load()
160 	data->crc = 0;  in fpga_ice40_load()
161 	data->loaded = false;  in fpga_ice40_load()
162 	fpga_ice40_crc_to_str(0, data->info);  in fpga_ice40_load()
165 	ret = gpio_pin_configure_dt(&config->cdone, GPIO_INPUT) ||  in fpga_ice40_load()
166 	      gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH) ||  in fpga_ice40_load()
167 	      gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH) ||  in fpga_ice40_load()
168 	      gpio_pin_configure_dt(&config_bitbang->clk, GPIO_OUTPUT_HIGH) ||  in fpga_ice40_load()
169 	      gpio_pin_configure_dt(&config_bitbang->pico, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
174 	*config_bitbang->clear |= (creset | cs);  in fpga_ice40_load()
177 	LOG_DBG("Delay %u us", config->creset_delay_us);  in fpga_ice40_load()
178 	fpga_ice40_delay(2 * config_bitbang->mhz_delay_count * config->creset_delay_us);  in fpga_ice40_load()
180 	if (gpio_pin_get_dt(&config->cdone) != 0) {  in fpga_ice40_load()
182 		ret = -EIO;  in fpga_ice40_load()
187 	*config_bitbang->set |= creset;  in fpga_ice40_load()
189 	LOG_DBG("Delay %u us", config->config_delay_us);  in fpga_ice40_load()
190 	k_busy_wait(config->config_delay_us);  in fpga_ice40_load()
193 	*config_bitbang->set |= cs;  in fpga_ice40_load()
195 	LOG_DBG("Send %u clocks", config->leading_clocks);  in fpga_ice40_load()
196 	fpga_ice40_send_clocks(config_bitbang->mhz_delay_count, config_bitbang->set,  in fpga_ice40_load()
197 			       config_bitbang->clear, clk, config->leading_clocks);  in fpga_ice40_load()
202 	fpga_ice40_spi_send_data(config_bitbang->mhz_delay_count, config_bitbang->set,  in fpga_ice40_load()
203 				 config_bitbang->clear, cs, clk, pico, (uint8_t *)image_ptr,  in fpga_ice40_load()
206 	LOG_DBG("Send %u clocks", config->trailing_clocks);  in fpga_ice40_load()
207 	fpga_ice40_send_clocks(config_bitbang->mhz_delay_count, config_bitbang->set,  in fpga_ice40_load()
208 			       config_bitbang->clear, clk, config->trailing_clocks);  in fpga_ice40_load()
211 	ret = gpio_pin_get_dt(&config->cdone);  in fpga_ice40_load()
216 		ret = -EIO;  in fpga_ice40_load()
222 	data->loaded = true;  in fpga_ice40_load()
223 	fpga_ice40_crc_to_str(crc, data->info);  in fpga_ice40_load()
227 	(void)gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
228 	(void)gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()
229 	(void)gpio_pin_configure_dt(&config_bitbang->clk, GPIO_DISCONNECTED);  in fpga_ice40_load()
230 	(void)gpio_pin_configure_dt(&config_bitbang->pico, GPIO_DISCONNECTED);  in fpga_ice40_load()
232 	(void)pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);  in fpga_ice40_load()
235 	k_spin_unlock(&data->lock, key);  in fpga_ice40_load()