Lines Matching +full:cs +full:- +full:mode
5 * SPDX-License-Identifier: Apache-2.0
17 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
27 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
61 * Delay before first Poll-1 command after suspend in 20 ns units
96 static inline void mchp_saf_cs_descr_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
99 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
102 static inline void mchp_saf_poll2_mask_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
105 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
106 if (cs == 0) { in mchp_saf_poll2_mask_wr()
107 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
109 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
113 static inline void mchp_saf_cm_prefix_wr(struct mchp_espi_saf *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
116 if (cs == 0) { in mchp_saf_cm_prefix_wr()
117 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
119 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
128 * Each protection region is composed of 4 32-bit registers
135 * address range and read-write-erase for all masters.
157 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
158 regs->SAF_PROT_RG[0].LIMIT = in saf_protection_regions_init()
159 regs->SAF_FL_CFG_SIZE_LIM >> 12; in saf_protection_regions_init()
160 regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL; in saf_protection_regions_init()
161 regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL; in saf_protection_regions_init()
163 regs->SAF_PROT_RG[n].START = in saf_protection_regions_init()
165 regs->SAF_PROT_RG[n].LIMIT = in saf_protection_regions_init()
167 regs->SAF_PROT_RG[n].WEBM = 0U; in saf_protection_regions_init()
168 regs->SAF_PROT_RG[n].RDBM = 0U; in saf_protection_regions_init()
171 LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START); in saf_protection_regions_init()
172 LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT); in saf_protection_regions_init()
173 LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM); in saf_protection_regions_init()
174 LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM); in saf_protection_regions_init()
185 return -EINVAL; in qmspi_freq_div()
190 return -EIO; in qmspi_freq_div()
209 * Take over and re-initialize QMSPI for use by SAF HW engine.
212 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
219 * 7. Enable QMSPI SAF mode
220 * 8. If user configuration overrides frequency, signalling mode,
222 * 9. Program QMSPI MODE and CSTIM registers with activate set.
228 struct qmspi_regs * const qregs = xcfg->qmspi_base; in saf_qmspi_init()
229 struct mchp_espi_saf * const regs = xcfg->saf_base; in saf_qmspi_init()
230 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg; in saf_qmspi_init()
232 qmode = qregs->MODE; in saf_qmspi_init()
234 return -EAGAIN; in saf_qmspi_init()
237 qmode = qregs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK); in saf_qmspi_init()
238 cstim = qregs->CSTM; in saf_qmspi_init()
239 qregs->MODE = MCHP_QMSPI_M_SRST; in saf_qmspi_init()
240 qregs->STS = MCHP_QMSPI_STS_RW1C_MASK; in saf_qmspi_init()
245 qregs->IFCTRL = in saf_qmspi_init()
250 qregs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] = in saf_qmspi_init()
251 hwcfg->generic_descr[n]; in saf_qmspi_init()
255 qregs->IEN = MCHP_QMSPI_IEN_XFR_DONE; in saf_qmspi_init()
260 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CPHA) { in saf_qmspi_init()
262 ((hwcfg->qmspi_cpha << MCHP_QMSPI_M_SIG_POS) & in saf_qmspi_init()
269 * QMSPI frequency divider in QMSPI.Mode register. Later we will update in saf_qmspi_init()
274 regs->SAF_CLKDIV_CS0 = qfdiv; in saf_qmspi_init()
275 regs->SAF_CLKDIV_CS1 = qfdiv; in saf_qmspi_init()
277 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CSTM) { in saf_qmspi_init()
278 cstim = hwcfg->qmspi_cs_timing; in saf_qmspi_init()
281 /* MEC172x SAF uses TX LDMA channel 0 in non-descriptor mode. in saf_qmspi_init()
287 qregs->LDTX[0].CTRL = MCHP_QMSPI_LDC_EN | MCHP_QMSPI_LDC_RS_EN | MCHP_QMSPI_LDC_ASZ_4; in saf_qmspi_init()
291 qregs->MODE = qmode; in saf_qmspi_init()
292 qregs->CSTM = cstim; in saf_qmspi_init()
314 regs->SAF_POLL_TMOUT = cfg->poll_timeout; in saf_flash_timing_init()
315 regs->SAF_POLL_INTRVL = cfg->poll_interval; in saf_flash_timing_init()
316 regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval; in saf_flash_timing_init()
317 regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout; in saf_flash_timing_init()
318 regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay; in saf_flash_timing_init()
319 LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT); in saf_flash_timing_init()
320 LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL); in saf_flash_timing_init()
321 LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL); in saf_flash_timing_init()
322 LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT); in saf_flash_timing_init()
323 LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY); in saf_flash_timing_init()
331 regs->SAF_DNX_PROT_BYP = 0; in saf_dnx_bypass_init()
332 regs->SAF_DNX_PROT_BYP = 0xffffffff; in saf_dnx_bypass_init()
344 const struct espi_saf_xec_config * const xcfg = dev->config; in saf_init_erase_block_size()
345 struct espi_iom_regs * const espi_iom = xcfg->iom_base; in saf_init_erase_block_size()
346 struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs; in saf_init_erase_block_size()
347 uint32_t opb = fcfg->opb; in saf_init_erase_block_size()
352 if (cfg->nflash_devices > 1) { in saf_init_erase_block_size()
354 opb &= fcfg->opb; in saf_init_erase_block_size()
359 return -EINVAL; in saf_init_erase_block_size()
370 espi_iom->SAFEBS = erase_bitmap; in saf_init_erase_block_size()
376 * Set the continuous mode prefix and 4-byte address mode bits
380 * SAF Flash Config Special Mode @ 0x1B0
383 static void saf_flash_misc_cfg(struct mchp_espi_saf * const regs, uint8_t cs, in saf_flash_misc_cfg() argument
388 d = regs->SAF_FL_CFG_MISC; in saf_flash_misc_cfg()
391 if (cs) { in saf_flash_misc_cfg()
395 /* Does this flash device require a prefix for continuous mode? */ in saf_flash_misc_cfg()
396 if (fcfg->cont_prefix != 0) { in saf_flash_misc_cfg()
403 if (cs) { in saf_flash_misc_cfg()
407 /* Use 32-bit addressing for this flash device? */ in saf_flash_misc_cfg()
408 if (fcfg->flags & MCHP_FLASH_FLAG_ADDR32) { in saf_flash_misc_cfg()
414 regs->SAF_FL_CFG_MISC = d; in saf_flash_misc_cfg()
418 static void saf_flash_pd_cfg(struct mchp_espi_saf * const regs, uint8_t cs, in saf_flash_pd_cfg() argument
424 if (cs == 0) { in saf_flash_pd_cfg()
426 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS0_EN) { in saf_flash_pd_cfg()
429 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS0_EC_WK_EN) { in saf_flash_pd_cfg()
434 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS1_EN) { in saf_flash_pd_cfg()
437 if (fcfg->flags & MCHP_FLASH_FLAG_V2_PD_CS1_EC_WK_EN) { in saf_flash_pd_cfg()
442 regs->SAF_PWRDN_CTRL = (regs->SAF_PWRDN_CTRL & ~msk) | pdval; in saf_flash_pd_cfg()
447 * Each divider register is composed of two 16-bit fields:
451 static int saf_flash_freq_cfg(struct mchp_espi_saf * const regs, uint8_t cs, in saf_flash_freq_cfg() argument
456 if (cs == 0) { in saf_flash_freq_cfg()
457 saf_qclk = regs->SAF_CLKDIV_CS0; in saf_flash_freq_cfg()
459 saf_qclk = regs->SAF_CLKDIV_CS1; in saf_flash_freq_cfg()
462 fmhz = fcfg->rd_freq_mhz; in saf_flash_freq_cfg()
468 return -EIO; in saf_flash_freq_cfg()
476 fmhz = fcfg->freq_mhz; in saf_flash_freq_cfg()
482 return -EIO; in saf_flash_freq_cfg()
490 if (cs == 0) { in saf_flash_freq_cfg()
491 regs->SAF_CLKDIV_CS0 = saf_qclk; in saf_flash_freq_cfg()
493 regs->SAF_CLKDIV_CS1 = saf_qclk; in saf_flash_freq_cfg()
507 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
513 const struct espi_saf_flash_cfg *fcfg, uint8_t cs) in saf_flash_cfg() argument
516 const struct espi_saf_xec_config * const xcfg = dev->config; in saf_flash_cfg()
517 struct mchp_espi_saf * const regs = xcfg->saf_base; in saf_flash_cfg()
518 struct qmspi_regs * const qregs = xcfg->qmspi_base; in saf_flash_cfg()
520 LOG_DBG("%s cs=%u", __func__, cs); in saf_flash_cfg()
522 regs->SAF_CS_OP[cs].OPA = fcfg->opa; in saf_flash_cfg()
523 regs->SAF_CS_OP[cs].OPB = fcfg->opb; in saf_flash_cfg()
524 regs->SAF_CS_OP[cs].OPC = fcfg->opc; in saf_flash_cfg()
525 regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids; in saf_flash_cfg()
528 if (cs != 0) { in saf_flash_cfg()
533 d = fcfg->descr[i] & ~(MCHP_QMSPI_C_NEXT_DESCR_MASK); in saf_flash_cfg()
536 qregs->DESCR[did++] = d; in saf_flash_cfg()
539 mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask); in saf_flash_cfg()
540 mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix); in saf_flash_cfg()
541 saf_flash_misc_cfg(regs, cs, fcfg); in saf_flash_cfg()
542 saf_flash_pd_cfg(regs, cs, fcfg); in saf_flash_cfg()
544 return saf_flash_freq_cfg(regs, cs, fcfg); in saf_flash_cfg()
554 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg; in saf_tagmap_init()
557 if (hwcfg->tag_map[i] & MCHP_SAF_HW_CFG_TAGMAP_USE) { in saf_tagmap_init()
558 regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i]; in saf_tagmap_init()
560 regs->SAF_TAG_MAP[i] = tag_map_dflt[i]; in saf_tagmap_init()
564 LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]); in saf_tagmap_init()
565 LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]); in saf_tagmap_init()
566 LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]); in saf_tagmap_init()
575 struct qmspi_regs * const qregs = xcfg->qmspi_base; in saf_qmspi_ldma_cfg()
576 uint32_t qmode = qregs->MODE; in saf_qmspi_ldma_cfg()
579 qregs->MODE = qmode & ~(MCHP_QMSPI_M_ACTIVATE); in saf_qmspi_ldma_cfg()
582 temp = qregs->DESCR[n]; in saf_qmspi_ldma_cfg()
586 chan--; /* register array index starts at 0 */ in saf_qmspi_ldma_cfg()
587 qregs->LDMA_TX_DESCR_BM |= BIT(n); in saf_qmspi_ldma_cfg()
588 qregs->LDTX[chan].CTRL = SAF_QSPI_LDMA_CTRL; in saf_qmspi_ldma_cfg()
594 chan--; in saf_qmspi_ldma_cfg()
595 qregs->LDMA_RX_DESCR_BM |= BIT(n); in saf_qmspi_ldma_cfg()
596 qregs->LDRX[chan].CTRL = SAF_QSPI_LDMA_CTRL; in saf_qmspi_ldma_cfg()
601 qregs->MODE = qmode; in saf_qmspi_ldma_cfg()
621 return -EINVAL; in espi_saf_xec_configuration()
624 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_xec_configuration()
625 struct mchp_espi_saf * const regs = xcfg->saf_base; in espi_saf_xec_configuration()
626 struct mchp_espi_saf_comm * const comm_regs = xcfg->saf_comm_base; in espi_saf_xec_configuration()
627 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg; in espi_saf_xec_configuration()
628 const struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs; in espi_saf_xec_configuration()
630 if ((fcfg == NULL) || (cfg->nflash_devices == 0U) || in espi_saf_xec_configuration()
631 (cfg->nflash_devices > MCHP_SAF_MAX_FLASH_DEVICES)) { in espi_saf_xec_configuration()
632 return -EINVAL; in espi_saf_xec_configuration()
635 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_configuration()
636 return -EAGAIN; in espi_saf_xec_configuration()
641 regs->SAF_CS0_CFG_P2M = 0; in espi_saf_xec_configuration()
642 regs->SAF_CS1_CFG_P2M = 0; in espi_saf_xec_configuration()
644 regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD; in espi_saf_xec_configuration()
647 regs->SAF_AC_RELOAD = hwcfg->flash_pd_timeout; in espi_saf_xec_configuration()
648 regs->SAF_FL_PWR_TMOUT = hwcfg->flash_pd_min_interval; in espi_saf_xec_configuration()
651 totalsz = fcfg->flashsz; in espi_saf_xec_configuration()
652 regs->SAF_FL_CFG_THRH = totalsz; in espi_saf_xec_configuration()
659 if (cfg->nflash_devices > 1) { in espi_saf_xec_configuration()
661 totalsz += fcfg->flashsz; in espi_saf_xec_configuration()
670 return -EAGAIN; in espi_saf_xec_configuration()
673 regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1; in espi_saf_xec_configuration()
676 regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM); in espi_saf_xec_configuration()
694 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEXP) { in espi_saf_xec_configuration()
698 regs->SAF_FL_CFG_MISC = in espi_saf_xec_configuration()
699 (regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u; in espi_saf_xec_configuration()
702 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEN) { in espi_saf_xec_configuration()
703 comm_regs->SAF_COMM_MODE |= MCHP_SAF_COMM_MODE_PF_EN; in espi_saf_xec_configuration()
705 comm_regs->SAF_COMM_MODE &= ~(MCHP_SAF_COMM_MODE_PF_EN); in espi_saf_xec_configuration()
708 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC); in espi_saf_xec_configuration()
710 comm_regs->SAF_COMM_MODE); in espi_saf_xec_configuration()
721 return -EINVAL; in espi_saf_xec_set_pr()
724 if (pr->nregions >= MCHP_ESPI_SAF_PR_MAX) { in espi_saf_xec_set_pr()
725 return -EINVAL; in espi_saf_xec_set_pr()
728 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_xec_set_pr()
729 struct mchp_espi_saf * const regs = xcfg->saf_base; in espi_saf_xec_set_pr()
731 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_set_pr()
732 return -EAGAIN; in espi_saf_xec_set_pr()
735 const struct espi_saf_pr *preg = pr->pregions; in espi_saf_xec_set_pr()
736 size_t n = pr->nregions; in espi_saf_xec_set_pr()
738 while (n--) { in espi_saf_xec_set_pr()
739 uint8_t regnum = preg->pr_num; in espi_saf_xec_set_pr()
742 return -EINVAL; in espi_saf_xec_set_pr()
746 if (preg->flags & MCHP_SAF_PR_FLAG_ENABLE) { in espi_saf_xec_set_pr()
747 regs->SAF_PROT_RG[regnum].START = preg->start >> 12U; in espi_saf_xec_set_pr()
748 regs->SAF_PROT_RG[regnum].LIMIT = in espi_saf_xec_set_pr()
749 (preg->start + preg->size - 1U) >> 12U; in espi_saf_xec_set_pr()
750 regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we; in espi_saf_xec_set_pr()
751 regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd; in espi_saf_xec_set_pr()
753 regs->SAF_PROT_RG[regnum].START = 0x7FFFFU; in espi_saf_xec_set_pr()
754 regs->SAF_PROT_RG[regnum].LIMIT = 0U; in espi_saf_xec_set_pr()
755 regs->SAF_PROT_RG[regnum].WEBM = 0U; in espi_saf_xec_set_pr()
756 regs->SAF_PROT_RG[regnum].RDBM = 0U; in espi_saf_xec_set_pr()
759 if (preg->flags & MCHP_SAF_PR_FLAG_LOCK) { in espi_saf_xec_set_pr()
760 regs->SAF_PROT_LOCK |= (1UL << regnum); in espi_saf_xec_set_pr()
771 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_xec_channel_ready()
772 struct mchp_espi_saf * const regs = xcfg->saf_base; in espi_saf_xec_channel_ready()
774 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_channel_ready()
808 const struct espi_saf_xec_config * const xcfg = dev->config; in get_erase_size_encoding()
809 struct espi_iom_regs * const espi_iom = xcfg->iom_base; in get_erase_size_encoding()
810 uint8_t supsz = espi_iom->SAFEBS; in get_erase_size_encoding()
829 return -EAGAIN; in check_ecp_access_size()
848 struct espi_saf_xec_data *xdat = dev->data; in saf_ecp_access()
849 const struct espi_saf_xec_config * const xcfg = dev->config; in saf_ecp_access()
850 struct mchp_espi_saf * const regs = xcfg->saf_base; in saf_ecp_access()
851 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[0]; in saf_ecp_access()
858 if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) { in saf_ecp_access()
860 return -EIO; in saf_ecp_access()
863 n = regs->SAF_ECP_BUSY; in saf_ecp_access()
866 return -EBUSY; in saf_ecp_access()
872 rc = check_ecp_access_size(pckt->len); in saf_ecp_access()
879 memcpy(slave_mem, pckt->buf, pckt->len); in saf_ecp_access()
882 n = pckt->len; in saf_ecp_access()
885 n = get_erase_size_encoding(dev, pckt->len); in saf_ecp_access()
888 return -EAGAIN; in saf_ecp_access()
893 rc = check_ecp_access_size(pckt->len); in saf_ecp_access()
898 if (!(regs->SAF_CFG_CS0_OPD & SAF_CFG_CS_OPC_RPMC_OP2_MSK)) { in saf_ecp_access()
900 return -EIO; in saf_ecp_access()
902 n = pckt->len; in saf_ecp_access()
906 rc = check_ecp_access_size(pckt->len); in saf_ecp_access()
911 if (!(regs->SAF_CFG_CS1_OPD & SAF_CFG_CS_OPC_RPMC_OP2_MSK)) { in saf_ecp_access()
913 return -EIO; in saf_ecp_access()
915 n = pckt->len; in saf_ecp_access()
919 return -EAGAIN; in saf_ecp_access()
924 regs->SAF_ECP_INTEN = 0; in saf_ecp_access()
925 regs->SAF_ECP_STATUS = MCHP_SAF_ECP_STS_MASK; in saf_ecp_access()
926 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos); in saf_ecp_access()
928 regs->SAF_ECP_INTEN = BIT(MCHP_SAF_ECP_INTEN_DONE_POS); in saf_ecp_access()
930 regs->SAF_ECP_FLAR = pckt->flash_addr; in saf_ecp_access()
931 regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0]; in saf_ecp_access()
937 LOG_DBG("%s ECP_FLAR=0x%x", __func__, regs->SAF_ECP_FLAR); in saf_ecp_access()
938 LOG_DBG("%s ECP_BFAR=0x%x", __func__, regs->SAF_ECP_BFAR); in saf_ecp_access()
941 regs->SAF_ECP_CMD = scmd; in saf_ecp_access()
942 regs->SAF_ECP_START = MCHP_SAF_ECP_START; in saf_ecp_access()
944 rc = k_sem_take(&xdat->ecp_lock, K_MSEC(MAX_SAF_FLASH_TIMEOUT_MS)); in saf_ecp_access()
945 if (rc == -EAGAIN) { in saf_ecp_access()
947 return -ETIMEDOUT; in saf_ecp_access()
952 n = regs->SAF_ECP_STATUS; in saf_ecp_access()
955 regs->SAF_ECP_STATUS = n; in saf_ecp_access()
957 return -EIO; in saf_ecp_access()
961 memcpy(pckt->buf, slave_mem, pckt->len); in saf_ecp_access()
993 struct espi_saf_xec_data *data = dev->data; in espi_saf_xec_manage_callback()
995 return espi_manage_callback(&data->callbacks, callback, set); in espi_saf_xec_manage_callback()
1001 return -EINVAL; in espi_saf_xec_activate()
1004 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_xec_activate()
1005 struct mchp_espi_saf * const regs = xcfg->saf_base; in espi_saf_xec_activate()
1006 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[1]; in espi_saf_xec_activate()
1008 regs->SAF_ESPI_MON_STATUS = MCHP_SAF_ESPI_MON_STS_IEN_MSK; in espi_saf_xec_activate()
1009 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos); in espi_saf_xec_activate()
1011 regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN; in espi_saf_xec_activate()
1012 regs->SAF_ESPI_MON_INTEN = (BIT(MCHP_SAF_ESPI_MON_STS_IEN_TMOUT_POS) | in espi_saf_xec_activate()
1025 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_done_isr()
1026 struct espi_saf_xec_data *data = dev->data; in espi_saf_done_isr()
1027 struct mchp_espi_saf * const regs = xcfg->saf_base; in espi_saf_done_isr()
1028 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[0]; in espi_saf_done_isr()
1029 uint32_t ecp_status = regs->SAF_ECP_STATUS; in espi_saf_done_isr()
1034 regs->SAF_ECP_INTEN = 0u; in espi_saf_done_isr()
1035 regs->SAF_ECP_STATUS = BIT(MCHP_SAF_ECP_STS_DONE_POS); in espi_saf_done_isr()
1036 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos); in espi_saf_done_isr()
1038 data->hwstatus = ecp_status; in espi_saf_done_isr()
1042 espi_send_callbacks(&data->callbacks, dev, evt); in espi_saf_done_isr()
1044 k_sem_give(&data->ecp_lock); in espi_saf_done_isr()
1049 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_err_isr()
1050 struct espi_saf_xec_data *data = dev->data; in espi_saf_err_isr()
1051 struct mchp_espi_saf * const regs = xcfg->saf_base; in espi_saf_err_isr()
1052 const struct espi_xec_irq_info *safirq = &xcfg->irq_info_list[1]; in espi_saf_err_isr()
1053 uint32_t mon_status = regs->SAF_ESPI_MON_STATUS; in espi_saf_err_isr()
1058 regs->SAF_ESPI_MON_STATUS = mon_status; in espi_saf_err_isr()
1059 mchp_xec_ecia_girq_src_clr(safirq->gid, safirq->gpos); in espi_saf_err_isr()
1061 data->hwstatus = mon_status; in espi_saf_err_isr()
1062 espi_send_callbacks(&data->callbacks, dev, evt); in espi_saf_err_isr()
1078 const struct espi_saf_xec_config * const xcfg = dev->config; in espi_saf_xec_init()
1079 struct espi_saf_xec_data * const data = dev->data; in espi_saf_xec_init()
1080 struct espi_iom_regs * const espi_iom = xcfg->iom_base; in espi_saf_xec_init()
1083 z_mchp_xec_pcr_periph_sleep(xcfg->pcr_idx, xcfg->pcr_pos, 0); in espi_saf_xec_init()
1086 espi_iom->CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP; in espi_saf_xec_init()
1087 espi_iom->CAPFC &= ~(MCHP_ESPI_FC_CAP_SHARE_MASK); in espi_saf_xec_init()
1088 espi_iom->CAPFC |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF; in espi_saf_xec_init()
1090 xcfg->irq_config_func(); in espi_saf_xec_init()
1092 k_sem_init(&data->ecp_lock, 0, 1); in espi_saf_xec_init()
1098 /* n = node-id, p = property, i = index */