1# Copyright 2023 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4description: |
5  NXP S32 Quad Serial Peripheral Interface (QSPI) Controller.
6
7  QSPI acts as an interface to up to two serial flash memory devices, each with
8  up to eight bidirectional bidirectional data lines, depending on the platform.
9
10compatible: "nxp,s32-qspi"
11
12include: [base.yaml, pinctrl-device.yaml]
13
14bus: qspi
15
16properties:
17  reg:
18    required: true
19
20  "#address-cells":
21    const: 1
22
23  "#size-cells":
24    const: 0
25
26  data-rate:
27    type: string
28    enum:
29      - SDR
30      - DDR
31    description: |
32      Selects the read mode:
33      - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34      - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
35
36  hold-time-2x:
37    type: boolean
38    description: |
39      Set to align incoming data with 2x serial flash half clock, when in DDR
40      mode. Otherwise, data will be aligned to the posedge of the controller's
41      internal reference clock.
42
43  sample-delay-half-cycle:
44    type: boolean
45    description: |
46      Set to use half-cycle early DQS delay when sampling received data.
47
48  sample-phase-inverted:
49    type: boolean
50    description: |
51      Set to sample received data at inverted clock.
52
53  cs-setup-time:
54    type: int
55    default: 3
56    description: |
57      Chip select setup time, in serial clock cycles. A bigger value will pull
58      the CS signal earlier before the transaction starts.
59      The default corresponds to the reset value of the register field.
60
61  cs-hold-time:
62    type: int
63    default: 3
64    description: |
65      Chip select hold time, in serial clock cycles. A bigger value will release
66      the CS signal later after the transaction ends.
67      The default corresponds to the reset value of the register field.
68
69  column-space:
70    type: int
71    default: 0
72    description: |
73      Column Address Space bit width. For example, if the column address is
74      [2:0] of QSPI_SFAR/AHB address, then the column address space bit width
75      must be 3. If there is no column address separation in any serial flash
76      device connected to this controller, this value must be programmed to 0.
77      The default corresponds to the reset value of the register field.
78
79  word-addressable:
80    type: boolean
81    description: |
82      Set if the serial flash device connected to this controller is word
83      (2 bytes) addressable.
84
85  byte-swapping:
86    type: boolean
87    description: |
88      In case of Octal DDR mode, specifies whether a word unit composed of two
89      bytes from posedge and negedge of a single DQS cycle needs to be swapped.
90
91  ahb-buffers-masters:
92    type: array
93    description: |
94      Masters ID's for the AHB receive buffers. The master ID of every incoming
95      request is checked and the data is returned or fetched into the
96      corresponding associated buffer. The maximum number of buffers is SoC
97      specific.
98
99  ahb-buffers-sizes:
100    type: array
101    description: |
102      Sizes (in bytes) of the AHB receive buffers. The maximum buffer size and
103      maximum number of buffers is SoC specific.
104
105  ahb-buffers-all-masters:
106    type: boolean
107    description: |
108      Any access from a master not associated with any other buffer is routed to
109      the last buffer.
110
111  a-rx-clock-source:
112    type: string
113    enum:
114      - LOOPBACK
115      - LOOPBACK DQS
116      - INTERNAL DQS
117      - EXTERNAL DQS
118    description: |
119      Selects DQS clock source for sampling read data at side A:
120      - LOOPBACK: use loopback clock from dummy internal PAD as strobe signal.
121      - LOOPBACK DQS: use loopback clock from PAD as strobe signal.
122      - INTERNAL DQS: use internally generated strobe signal.
123      - EXTERNAL DQS: use external strobe signal.
124
125  a-io2-idle-high:
126    type: boolean
127    description: |
128      Set if the logic level of IO2 signal output of this controller must be
129      driven high in the inactive state.
130      This property applies to side A of the controller.
131
132  a-io3-idle-high:
133    type: boolean
134    description: |
135      Set if the logic level of IO3 signal output of this controller must be
136      driven high in the inactive state.
137      This property applies to side A of the controller.
138
139  a-dll-mode:
140    type: string
141    enum:
142      - BYPASSED
143      - MANUAL UPDATE
144      - AUTO UPDATE
145    default: BYPASSED
146    description: |
147      DLL mode. The supported modes depends on the SoC.
148      This property applies to side A of the controller.
149
150  a-dll-freq-enable:
151    type: boolean
152    description: |
153      Selects delay-chain for high frequency of operation.
154      This property applies to side A of the controller.
155
156  a-dll-ref-counter:
157    type: int
158    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
159    default: 1
160    description: |
161      Select the "n+1" interval of DLL phase detection and reference delay
162      updating interval.
163      Minimum recommended value is 1 (reset value).
164      This property applies to side A of the controller.
165
166  a-dll-resolution:
167    type: int
168    enum: [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
169    default: 2
170    description: |
171      Minimum resolution for DLL phase detector to remain locked/unlocked based
172      on flash memory clock jitter.
173      The minimum value is 2 (reset value).
174      This property applies to side A of the controller.
175
176  a-dll-coarse-delay:
177    type: int
178    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
179    default: 0
180    description: |
181      This field sets the number of delay elements in each delay tap. The field
182      is used to overwrite DLL-generated delay values.
183      Default to 0 (reset value).
184      This property applies to side A of the controller.
185
186  a-dll-fine-delay:
187    type: int
188    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
189    default: 0
190    description: |
191      This field sets the number of fine offset delay elements up to 16 in
192      incoming DQS.
193      Default to 0 (reset value).
194      This property applies to side A of the controller.
195
196  a-dll-tap-select:
197    type: int
198    enum: [0, 1, 2, 3, 4, 5, 6, 7]
199    default: 0
200    description: |
201      Selects the Nth tap provided by the slave delay-chain.
202      Default to 0 (reset value).
203      This property applies to side A of the controller.
204
205child-binding:
206  description: NXP S32 QuadSPI port
207
208  include: nxp,s32-qspi-device.yaml
209