Lines Matching +full:cs +full:- +full:mode
2 # SPDX-License-Identifier: Apache-2.0
10 compatible: "nxp,s32-qspi"
12 include: [base.yaml, pinctrl-device.yaml]
20 "#address-cells":
23 "#size-cells":
26 data-rate:
29 - SDR
30 - DDR
32 Selects the read mode:
33 - Single Data Rate (SDR): sampling of incoming data occurs on single edges.
34 - Double Data Rate (DDR): sampling of incoming data occurs on both edges.
36 hold-time-2x:
40 mode. Otherwise, data will be aligned to the posedge of the controller's
43 sample-delay-half-cycle:
46 Set to use half-cycle early DQS delay when sampling received data.
48 sample-phase-inverted:
53 cs-setup-time:
58 the CS signal earlier before the transaction starts.
61 cs-hold-time:
66 the CS signal later after the transaction ends.
69 column-space:
79 word-addressable:
85 byte-swapping:
88 In case of Octal DDR mode, specifies whether a word unit composed of two
91 ahb-buffers-masters:
99 ahb-buffers-sizes:
105 ahb-buffers-all-masters:
111 a-rx-clock-source:
114 - LOOPBACK
115 - LOOPBACK DQS
116 - INTERNAL DQS
117 - EXTERNAL DQS
120 - LOOPBACK: use loopback clock from dummy internal PAD as strobe signal.
121 - LOOPBACK DQS: use loopback clock from PAD as strobe signal.
122 - INTERNAL DQS: use internally generated strobe signal.
123 - EXTERNAL DQS: use external strobe signal.
125 a-io2-idle-high:
132 a-io3-idle-high:
139 a-dll-mode:
142 - BYPASSED
143 - MANUAL UPDATE
144 - AUTO UPDATE
147 DLL mode. The supported modes depends on the SoC.
150 a-dll-freq-enable:
153 Selects delay-chain for high frequency of operation.
156 a-dll-ref-counter:
166 a-dll-resolution:
176 a-dll-coarse-delay:
182 is used to overwrite DLL-generated delay values.
186 a-dll-fine-delay:
196 a-dll-tap-select:
201 Selects the Nth tap provided by the slave delay-chain.
205 child-binding:
208 include: nxp,s32-qspi-device.yaml