Lines Matching +full:cs +full:- +full:mode
5 * SPDX-License-Identifier: Apache-2.0
20 /* SAF EC Portal read/write flash access limited to 1-64 bytes */
44 * Delay before first Poll-1 command after suspend in 20 ns units
72 static inline void mchp_saf_cs_descr_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cs_descr_wr() argument
75 regs->SAF_CS_OP[cs].OP_DESCR = val; in mchp_saf_cs_descr_wr()
78 static inline void mchp_saf_poll2_mask_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_poll2_mask_wr() argument
81 LOG_DBG("%s cs: %d mask %x", __func__, cs, val); in mchp_saf_poll2_mask_wr()
82 if (cs == 0) { in mchp_saf_poll2_mask_wr()
83 regs->SAF_CS0_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
85 regs->SAF_CS1_CFG_P2M = val; in mchp_saf_poll2_mask_wr()
89 static inline void mchp_saf_cm_prefix_wr(MCHP_SAF_HW_REGS *regs, uint8_t cs, in mchp_saf_cm_prefix_wr() argument
92 if (cs == 0) { in mchp_saf_cm_prefix_wr()
93 regs->SAF_CS0_CM_PRF = val; in mchp_saf_cm_prefix_wr()
95 regs->SAF_CS1_CM_PRF = val; in mchp_saf_cm_prefix_wr()
105 return -ETIMEDOUT; in xec_saf_spin_yield()
122 * Each protection region is composed of 4 32-bit registers
129 * address range and read-write-erase for all masters.
151 regs->SAF_PROT_RG[0].START = 0U; in saf_protection_regions_init()
152 regs->SAF_PROT_RG[0].LIMIT = in saf_protection_regions_init()
153 regs->SAF_FL_CFG_SIZE_LIM >> 12; in saf_protection_regions_init()
154 regs->SAF_PROT_RG[0].WEBM = MCHP_SAF_MSTR_ALL; in saf_protection_regions_init()
155 regs->SAF_PROT_RG[0].RDBM = MCHP_SAF_MSTR_ALL; in saf_protection_regions_init()
157 regs->SAF_PROT_RG[n].START = in saf_protection_regions_init()
159 regs->SAF_PROT_RG[n].LIMIT = in saf_protection_regions_init()
161 regs->SAF_PROT_RG[n].WEBM = 0U; in saf_protection_regions_init()
162 regs->SAF_PROT_RG[n].RDBM = 0U; in saf_protection_regions_init()
165 LOG_DBG("PROT[%d] START %x", n, regs->SAF_PROT_RG[n].START); in saf_protection_regions_init()
166 LOG_DBG("PROT[%d] LIMIT %x", n, regs->SAF_PROT_RG[n].LIMIT); in saf_protection_regions_init()
167 LOG_DBG("PROT[%d] WEBM %x", n, regs->SAF_PROT_RG[n].WEBM); in saf_protection_regions_init()
168 LOG_DBG("PROT[%d] RDBM %x", n, regs->SAF_PROT_RG[n].RDBM); in saf_protection_regions_init()
177 fdiv = 0U; /* freq divider field -> 256 */ in qmspi_freq_div()
192 * Take over and re-initialize QMSPI for use by SAF HW engine.
195 * 1. Save QMSPI driver frequency divider, SPI signalling mode, and
202 * 7. Enable QMSPI SAF mode
203 * 8. If user configuration overrides frequency, signalling mode,
205 * 9. Program QMSPI MODE and CSTIM registers with activate set.
211 QMSPI_Type *regs = (QMSPI_Type *)xcfg->qmspi_base_addr; in saf_qmspi_init()
212 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg; in saf_qmspi_init()
214 qmode = regs->MODE; in saf_qmspi_init()
216 return -EAGAIN; in saf_qmspi_init()
219 qmode = regs->MODE & (MCHP_QMSPI_M_FDIV_MASK | MCHP_QMSPI_M_SIG_MASK); in saf_qmspi_init()
220 cstim = regs->CSTM; in saf_qmspi_init()
221 regs->MODE = MCHP_QMSPI_M_SRST; in saf_qmspi_init()
222 regs->STS = MCHP_QMSPI_STS_RW1C_MASK; in saf_qmspi_init()
227 regs->IFCTRL = in saf_qmspi_init()
232 regs->DESCR[MCHP_SAF_CM_EXIT_START_DESCR + n] = in saf_qmspi_init()
233 hwcfg->generic_descr[n]; in saf_qmspi_init()
236 regs->IEN = MCHP_QMSPI_IEN_XFR_DONE; in saf_qmspi_init()
241 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CPHA) { in saf_qmspi_init()
243 ((hwcfg->qmspi_cpha << MCHP_QMSPI_M_SIG_POS) & in saf_qmspi_init()
247 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_FREQ) { in saf_qmspi_init()
249 qmspi_freq_div(hwcfg->qmspi_freq_hz); in saf_qmspi_init()
252 if (hwcfg->flags & MCHP_SAF_HW_CFG_FLAG_CSTM) { in saf_qmspi_init()
253 cstim = hwcfg->qmspi_cs_timing; in saf_qmspi_init()
256 regs->MODE = qmode; in saf_qmspi_init()
257 regs->CSTM = cstim; in saf_qmspi_init()
279 regs->SAF_POLL_TMOUT = cfg->poll_timeout; in saf_flash_timing_init()
280 regs->SAF_POLL_INTRVL = cfg->poll_interval; in saf_flash_timing_init()
281 regs->SAF_SUS_RSM_INTRVL = cfg->sus_rsm_interval; in saf_flash_timing_init()
282 regs->SAF_CONSEC_RD_TMOUT = cfg->consec_rd_timeout; in saf_flash_timing_init()
283 regs->SAF_SUS_CHK_DLY = cfg->sus_chk_delay; in saf_flash_timing_init()
284 LOG_DBG("SAF_POLL_TMOUT %x\n", regs->SAF_POLL_TMOUT); in saf_flash_timing_init()
285 LOG_DBG("SAF_POLL_INTRVL %x\n", regs->SAF_POLL_INTRVL); in saf_flash_timing_init()
286 LOG_DBG("SAF_SUS_RSM_INTRVL %x\n", regs->SAF_SUS_RSM_INTRVL); in saf_flash_timing_init()
287 LOG_DBG("SAF_CONSEC_RD_TMOUT %x\n", regs->SAF_CONSEC_RD_TMOUT); in saf_flash_timing_init()
288 LOG_DBG("SAF_SUS_CHK_DLY %x\n", regs->SAF_SUS_CHK_DLY); in saf_flash_timing_init()
296 regs->SAF_DNX_PROT_BYP = 0; in saf_dnx_bypass_init()
297 regs->SAF_DNX_PROT_BYP = 0xffffffff; in saf_dnx_bypass_init()
309 struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs; in saf_init_erase_block_size()
310 uint32_t opb = fcfg->opb; in saf_init_erase_block_size()
315 if (cfg->nflash_devices > 1) { in saf_init_erase_block_size()
317 opb &= fcfg->opb; in saf_init_erase_block_size()
322 return -EINVAL; in saf_init_erase_block_size()
333 ESPI_CAP_REGS->FC_SERBZ = erase_bitmap; in saf_init_erase_block_size()
339 * Set the continuous mode prefix and 4-byte address mode bits
343 * SAF Flash Config Special Mode @ 0x1B0
346 static void saf_flash_misc_cfg(MCHP_SAF_HW_REGS *regs, uint8_t cs, in saf_flash_misc_cfg() argument
351 d = regs->SAF_FL_CFG_MISC; in saf_flash_misc_cfg()
354 if (cs) { in saf_flash_misc_cfg()
358 /* Does this flash device require a prefix for continuous mode? */ in saf_flash_misc_cfg()
359 if (fcfg->cont_prefix != 0) { in saf_flash_misc_cfg()
366 if (cs) { in saf_flash_misc_cfg()
370 /* Use 32-bit addressing for this flash device? */ in saf_flash_misc_cfg()
371 if (fcfg->flags & MCHP_FLASH_FLAG_ADDR32) { in saf_flash_misc_cfg()
377 regs->SAF_FL_CFG_MISC = d; in saf_flash_misc_cfg()
389 * CS0: QMSPI descriptors 0-5 or CS1 QMSPI descriptors 6-11
393 const struct espi_saf_flash_cfg *fcfg, uint8_t cs) in saf_flash_cfg() argument
396 const struct espi_saf_xec_config *xcfg = dev->config; in saf_flash_cfg()
397 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr; in saf_flash_cfg()
398 QMSPI_Type *qregs = (QMSPI_Type *)xcfg->qmspi_base_addr; in saf_flash_cfg()
400 LOG_DBG("%s cs=%u", __func__, cs); in saf_flash_cfg()
402 regs->SAF_CS_OP[cs].OPA = fcfg->opa; in saf_flash_cfg()
403 regs->SAF_CS_OP[cs].OPB = fcfg->opb; in saf_flash_cfg()
404 regs->SAF_CS_OP[cs].OPC = fcfg->opc; in saf_flash_cfg()
405 regs->SAF_CS_OP[cs].OP_DESCR = (uint32_t)fcfg->cs_cfg_descr_ids; in saf_flash_cfg()
408 if (cs != 0) { in saf_flash_cfg()
413 d = fcfg->descr[i] & ~(MCHP_QMSPI_C_NEXT_DESCR_MASK); in saf_flash_cfg()
416 qregs->DESCR[did++] = d; in saf_flash_cfg()
419 mchp_saf_poll2_mask_wr(regs, cs, fcfg->poll2_mask); in saf_flash_cfg()
420 mchp_saf_cm_prefix_wr(regs, cs, fcfg->cont_prefix); in saf_flash_cfg()
421 saf_flash_misc_cfg(regs, cs, fcfg); in saf_flash_cfg()
431 const struct espi_saf_hw_cfg *hwcfg = &cfg->hwcfg; in saf_tagmap_init()
434 if (hwcfg->tag_map[i] & MCHP_SAF_HW_CFG_TAGMAP_USE) { in saf_tagmap_init()
435 regs->SAF_TAG_MAP[i] = hwcfg->tag_map[i]; in saf_tagmap_init()
437 regs->SAF_TAG_MAP[i] = tag_map_dflt[i]; in saf_tagmap_init()
441 LOG_DBG("SAF TAG0 %x", regs->SAF_TAG_MAP[0]); in saf_tagmap_init()
442 LOG_DBG("SAF TAG1 %x", regs->SAF_TAG_MAP[1]); in saf_tagmap_init()
443 LOG_DBG("SAF TAG2 %x", regs->SAF_TAG_MAP[2]); in saf_tagmap_init()
463 return -EINVAL; in espi_saf_xec_configuration()
466 const struct espi_saf_xec_config *xcfg = dev->config; in espi_saf_xec_configuration()
467 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr; in espi_saf_xec_configuration()
468 const struct espi_saf_flash_cfg *fcfg = cfg->flash_cfgs; in espi_saf_xec_configuration()
470 if ((fcfg == NULL) || (cfg->nflash_devices == 0U) || in espi_saf_xec_configuration()
471 (cfg->nflash_devices > MCHP_SAF_MAX_FLASH_DEVICES)) { in espi_saf_xec_configuration()
472 return -EINVAL; in espi_saf_xec_configuration()
475 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_configuration()
476 return -EAGAIN; in espi_saf_xec_configuration()
481 regs->SAF_CS0_CFG_P2M = 0; in espi_saf_xec_configuration()
482 regs->SAF_CS1_CFG_P2M = 0; in espi_saf_xec_configuration()
484 regs->SAF_FL_CFG_GEN_DESCR = MCHP_SAF_FL_CFG_GEN_DESCR_STD; in espi_saf_xec_configuration()
487 totalsz = fcfg->flashsz; in espi_saf_xec_configuration()
488 regs->SAF_FL_CFG_THRH = totalsz; in espi_saf_xec_configuration()
492 if (cfg->nflash_devices > 1) { in espi_saf_xec_configuration()
494 totalsz += fcfg->flashsz; in espi_saf_xec_configuration()
500 return -EAGAIN; in espi_saf_xec_configuration()
503 regs->SAF_FL_CFG_SIZE_LIM = totalsz - 1; in espi_saf_xec_configuration()
506 regs->SAF_FL_CFG_THRH, regs->SAF_FL_CFG_SIZE_LIM); in espi_saf_xec_configuration()
524 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEXP) { in espi_saf_xec_configuration()
528 regs->SAF_FL_CFG_MISC = in espi_saf_xec_configuration()
529 (regs->SAF_FL_CFG_MISC & ~(MCHP_SAF_FL_CFG_MISC_PFOE_MASK)) | u; in espi_saf_xec_configuration()
532 if (cfg->hwcfg.flags & MCHP_SAF_HW_CFG_FLAG_PFEN) { in espi_saf_xec_configuration()
538 LOG_DBG("%s SAF_FL_CFG_MISC: %x", __func__, regs->SAF_FL_CFG_MISC); in espi_saf_xec_configuration()
549 return -EINVAL; in espi_saf_xec_set_pr()
552 if (pr->nregions >= MCHP_ESPI_SAF_PR_MAX) { in espi_saf_xec_set_pr()
553 return -EINVAL; in espi_saf_xec_set_pr()
556 const struct espi_saf_xec_config *xcfg = dev->config; in espi_saf_xec_set_pr()
557 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)xcfg->saf_base_addr; in espi_saf_xec_set_pr()
559 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_set_pr()
560 return -EAGAIN; in espi_saf_xec_set_pr()
563 const struct espi_saf_pr *preg = pr->pregions; in espi_saf_xec_set_pr()
564 size_t n = pr->nregions; in espi_saf_xec_set_pr()
566 while (n--) { in espi_saf_xec_set_pr()
567 uint8_t regnum = preg->pr_num; in espi_saf_xec_set_pr()
570 return -EINVAL; in espi_saf_xec_set_pr()
574 if (preg->flags & MCHP_SAF_PR_FLAG_ENABLE) { in espi_saf_xec_set_pr()
575 regs->SAF_PROT_RG[regnum].START = preg->start >> 12U; in espi_saf_xec_set_pr()
576 regs->SAF_PROT_RG[regnum].LIMIT = in espi_saf_xec_set_pr()
577 (preg->start + preg->size - 1U) >> 12U; in espi_saf_xec_set_pr()
578 regs->SAF_PROT_RG[regnum].WEBM = preg->master_bm_we; in espi_saf_xec_set_pr()
579 regs->SAF_PROT_RG[regnum].RDBM = preg->master_bm_rd; in espi_saf_xec_set_pr()
581 regs->SAF_PROT_RG[regnum].START = 0x7FFFFU; in espi_saf_xec_set_pr()
582 regs->SAF_PROT_RG[regnum].LIMIT = 0U; in espi_saf_xec_set_pr()
583 regs->SAF_PROT_RG[regnum].WEBM = 0U; in espi_saf_xec_set_pr()
584 regs->SAF_PROT_RG[regnum].RDBM = 0U; in espi_saf_xec_set_pr()
587 if (preg->flags & MCHP_SAF_PR_FLAG_LOCK) { in espi_saf_xec_set_pr()
588 regs->SAF_PROT_LOCK |= (1UL << regnum); in espi_saf_xec_set_pr()
599 const struct espi_saf_xec_config *cfg = dev->config; in espi_saf_xec_channel_ready()
600 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr; in espi_saf_xec_channel_ready()
602 if (regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN) { in espi_saf_xec_channel_ready()
636 uint8_t supsz = ESPI_CAP_REGS->FC_SERBZ; in get_erase_size_encoding()
655 return -EAGAIN; in check_ecp_access_size()
672 struct espi_saf_xec_data *xdat = dev->data; in saf_ecp_access()
673 const struct espi_saf_xec_config *cfg = dev->config; in saf_ecp_access()
674 MCHP_SAF_HW_REGS *regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr; in saf_ecp_access()
681 if (!(regs->SAF_FL_CFG_MISC & MCHP_SAF_FL_CFG_MISC_SAF_EN)) { in saf_ecp_access()
683 return -EIO; in saf_ecp_access()
686 if (regs->SAF_ECP_BUSY & MCHP_SAF_ECP_BUSY) { in saf_ecp_access()
688 return -EBUSY; in saf_ecp_access()
693 rc = check_ecp_access_size(pckt->len); in saf_ecp_access()
700 memcpy(slave_mem, pckt->buf, pckt->len); in saf_ecp_access()
703 n = pckt->len; in saf_ecp_access()
705 n = get_erase_size_encoding(pckt->len); in saf_ecp_access()
708 return -EAGAIN; in saf_ecp_access()
712 return -EAGAIN; in saf_ecp_access()
717 k_sem_take(&xdat->ecp_lock, K_FOREVER); in saf_ecp_access()
719 regs->SAF_ECP_INTEN = 0; in saf_ecp_access()
720 regs->SAF_ECP_STATUS = 0xffffffff; in saf_ecp_access()
723 * TODO - Force SAF Done interrupt disabled until we have support in saf_ecp_access()
729 regs->SAF_ECP_FLAR = pckt->flash_addr; in saf_ecp_access()
730 regs->SAF_ECP_BFAR = (uint32_t)&slave_mem[0]; in saf_ecp_access()
732 regs->SAF_ECP_CMD = in saf_ecp_access()
738 regs->SAF_ECP_START = MCHP_SAF_ECP_START; in saf_ecp_access()
745 xdat->hwstatus = regs->SAF_ECP_STATUS; in saf_ecp_access()
746 while (!(xdat->hwstatus & MCHP_SAF_ECP_STS_DONE)) { in saf_ecp_access()
751 xdat->hwstatus = regs->SAF_ECP_STATUS; in saf_ecp_access()
755 regs->SAF_ECP_STATUS = xdat->hwstatus; in saf_ecp_access()
756 if (xdat->hwstatus & MCHP_SAF_ECP_STS_ERR_MASK) { in saf_ecp_access()
757 rc = -EIO; in saf_ecp_access()
762 memcpy(pckt->buf, slave_mem, pckt->len); in saf_ecp_access()
766 k_sem_give(&xdat->ecp_lock); in saf_ecp_access()
797 struct espi_saf_xec_data *data = dev->data; in espi_saf_xec_manage_callback()
799 return espi_manage_callback(&data->callbacks, callback, set); in espi_saf_xec_manage_callback()
808 return -EINVAL; in espi_saf_xec_activate()
811 cfg = dev->config; in espi_saf_xec_activate()
812 regs = (MCHP_SAF_HW_REGS *)cfg->saf_base_addr; in espi_saf_xec_activate()
814 regs->SAF_FL_CFG_MISC |= MCHP_SAF_FL_CFG_MISC_SAF_EN; in espi_saf_xec_activate()
856 struct espi_saf_xec_data *data = dev->data; in espi_saf_xec_init()
865 ESPI_CAP_REGS->GLB_CAP0 |= MCHP_ESPI_GBL_CAP0_FC_SUPP; in espi_saf_xec_init()
866 ESPI_CAP_REGS->FC_CAP &= ~(MCHP_ESPI_FC_CAP_SHARE_MASK); in espi_saf_xec_init()
867 ESPI_CAP_REGS->FC_CAP |= MCHP_ESPI_FC_CAP_SHARE_MAF_SAF; in espi_saf_xec_init()
869 k_sem_init(&data->ecp_lock, 1, 1); in espi_saf_xec_init()