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/Zephyr-latest/drivers/modem/
DKconfig.hl780079 bool "Band 1 (2000MHz)"
82 Enable Band 1 (2000MHz)
85 bool "Band 2 (1900MHz)"
88 Enable Band 2 (1900MHz)
91 bool "Band 3 (1800MHz)"
94 Enable Band 3 (1800MHz)
97 bool "Band 4 (1700MHz)"
100 Enable Band 4 (1700MHz)
103 bool "Band 5 (850MHz)"
106 Enable Band 5 (850MHz)
[all …]
/Zephyr-latest/dts/bindings/clock/
Dst,stm32u5-msi-clock.yaml22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
Dst,stm32c0-hsi-clock.yaml6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
Dst,stm32g0-hsi-clock.yaml6 On STM32G0, HSI is a 16MHz fixed clock.
12 - 1 ==> HSISYS = 16MHZ
13 - 2 ==> HSISYS = 8MHZ
14 - 4 ==> HSISYS = 4MHZ
15 - 8 ==> HSISYS = 2MHZ
16 - 16 ==> HSISYS = 1MHZ
17 - 32 ==> HSISYS = 0.5MHz
18 - 64 ==> HSISYS = 0.25MHZ
19 - 128 ==> HSISYS = 0.125MHz
Dnuvoton,npcm-pcc.yaml14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
38 100000000, 100 MHz
39 96000000, 96 MHz
[all …]
Dnuvoton,npcx-pcc.yaml14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
35 120000000, 120 MHz
36 100000000, 100 MHz
37 96000000, 96 MHz
38 90000000, 90 MHz
39 80000000, 80 MHz
[all …]
Dst,stm32-msi-clock.yaml23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
/Zephyr-latest/samples/sensor/fdc2x1x/
DREADME.rst63 ch0: 5.318888 MHz ch1: 5.150293 MHz
66 ch0: 5.318819 MHz ch1: 5.150307 MHz
69 ch0: 5.318822 MHz ch1: 5.150200 MHz
72 ch0: 5.318752 MHz ch1: 5.150265 MHz
83 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
86 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
89 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
92 ch0: 4.966171 MHz ch1: 4.946465 MHz ch2: 4.985879 MHz ch3: 4.907051 MHz
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dclock.c20 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk / in soc_early_init_hook()
22 * - 16 MHz (bypass HFPLL). in soc_early_init_hook()
23 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL). in soc_early_init_hook()
25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
36 /* refr = 8 MHz. */ in soc_early_init_hook()
40 /* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */ in soc_early_init_hook()
41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c13 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
26 * - core: to 1GHz PLL (CORE_PLL) from 26MHz oscillator (HFCLK)
27 * - peri: to 250MHz PLL (HFPCLKPLL) from HFCLK
28 * - ddr: to 923MHz PLL (DDRPLL) from HFCLK (half of the data rate)
31 * Note: Valid PLL VCO range is 2400MHz to 4800MHz
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
38 PLL_F(76) | /* VCO: 2 x (76 + 1) = 154 = 4004MHz */ in soc_early_init_hook()
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()
40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
[all …]
/Zephyr-latest/subsys/lorawan/
DKconfig48 bool "Asia 923MHz Frequency band"
51 bool "Australia 915MHz Frequency band"
54 bool "China 470MHz Frequency band"
57 bool "China 779MHz Frequency band"
60 bool "Europe 433MHz Frequency band"
63 bool "Europe 868MHz Frequency band"
66 bool "South Korea 920MHz Frequency band"
69 bool "India 865MHz Frequency band"
72 bool "North America 915MHz Frequency band"
75 bool "Russia 864MHz Frequency band"
/Zephyr-latest/boards/nxp/mimxrt1024_evk/
Dmimxrt1024_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
29 nxp,speed = "50-mhz";
43 nxp,speed = "200-mhz";
49 nxp,speed = "100-mhz";
61 nxp,speed = "200-mhz";
69 nxp,speed = "100-mhz";
77 nxp,speed = "100-mhz";
91 nxp,speed = "100-mhz";
103 nxp,speed = "100-mhz";
115 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1062_fmurt6/
Dmimxrt1062_fmurt6-pinctrl.dtsi19 nxp,speed = "100-mhz";
28 nxp,speed = "50-mhz";
43 nxp,speed = "200-mhz";
50 nxp,speed = "200-mhz";
58 nxp,speed = "50-mhz";
68 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
88 nxp,speed = "100-mhz";
99 nxp,speed = "200-mhz";
109 nxp,speed = "200-mhz";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1064_evk/
Dmimxrt1064_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
59 nxp,speed = "50-mhz";
74 nxp,speed = "200-mhz";
88 nxp,speed = "200-mhz";
98 nxp,speed = "100-mhz";
109 nxp,speed = "100-mhz";
119 nxp,speed = "100-mhz";
129 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dsoc.c98 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
126 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
128 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/boards/pjrc/teensy4/
Dteensy4-pinctrl.dtsi20 nxp,speed = "100-mhz";
35 nxp,speed = "200-mhz";
49 nxp,speed = "200-mhz";
60 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
84 nxp,speed = "100-mhz";
97 nxp,speed = "100-mhz";
110 nxp,speed = "100-mhz";
123 nxp,speed = "100-mhz";
137 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1020_evk/
Dmimxrt1020_evk-pinctrl.dtsi19 nxp,speed = "100-mhz";
30 nxp,speed = "50-mhz";
44 nxp,speed = "200-mhz";
50 nxp,speed = "100-mhz";
62 nxp,speed = "200-mhz";
70 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
92 nxp,speed = "100-mhz";
104 nxp,speed = "100-mhz";
116 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/boards/nxp/mimxrt1060_evk/
Dmimxrt1060_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
59 nxp,speed = "50-mhz";
74 nxp,speed = "200-mhz";
88 nxp,speed = "200-mhz";
98 nxp,speed = "100-mhz";
109 nxp,speed = "100-mhz";
121 nxp,speed = "100-mhz";
133 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/dts/bindings/cpu/
Despressif,xtensa-lx6.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz
Despressif,xtensa-lx7.yaml16 - 0: ESP32_CPU_CLK_SRC_XTAL - Uses the external crystal clock typically at 40 MHz.
18 320 MHz or 480 MHz.
20 frequency of 17.5 MHz. 8 MHz for ESP32S2.
21 - 3: APLL_CLK - 16 Mhz ~ 128 MHz (ESP32S2 Only)
/Zephyr-latest/boards/nxp/mimxrt1050_evk/
Dmimxrt1050_evk-pinctrl.dtsi20 nxp,speed = "100-mhz";
32 nxp,speed = "100-mhz";
49 nxp,speed = "100-mhz";
59 nxp,speed = "50-mhz";
74 nxp,speed = "200-mhz";
88 nxp,speed = "200-mhz";
98 nxp,speed = "100-mhz";
109 nxp,speed = "100-mhz";
119 nxp,speed = "100-mhz";
131 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/drivers/spi/
Dspi_esp32_spim.h17 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) /* 8.89MHz */
18 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) /* 10MHz */
19 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) /* 11.43MHz */
20 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) /* 13.33MHz */
21 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) /* 16MHz */
22 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) /* 20MHz */
23 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) /* 26.67MHz */
24 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) /* 40MHz */
25 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) /* 80MHz */
/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dsoc.c64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
119 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
123 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
[all …]
/Zephyr-latest/boards/madmachine/mm_swiftio/
Dmm_swiftio-pinctrl.dtsi28 nxp,speed = "100-mhz";
39 nxp,speed = "100-mhz";
51 nxp,speed = "100-mhz";
61 nxp,speed = "100-mhz";
72 nxp,speed = "100-mhz";
78 nxp,speed = "100-mhz";
89 nxp,speed = "100-mhz";
103 nxp,speed = "100-mhz";
112 nxp,speed = "100-mhz";
118 nxp,speed = "100-mhz";
[all …]
/Zephyr-latest/dts/bindings/pinctrl/
Dnxp,s32ze-pinctrl.yaml102 0: FMAX_3318 = 208 MHz (at 1.8 V), 166 MHz (at 3.3 V)
103 4: FMAX_3318 = 166 MHz (at 1.8 V), 150 MHz (at 3.3 V)
104 5: FMAX_3318 = 150 MHz (at 1.8 V), 133 MHz (at 3.3 V)
105 6: FMAX_3318 = 133 MHz (at 1.8 V), 100 MHz (at 3.3 V)
106 7: FMAX_3318 = 100 MHz (at 1.8 V), 83 MHz (at 3.3 V)
108 0: FMAX_18 = 208 MHz
109 4: FMAX_18 = 150 MHz
110 5: FMAX_18 = 133 MHz
111 6: FMAX_18 = 100 MHz
112 7: FMAX_18 = 50 MHz
[all …]

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