Lines Matching full:mhz
64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
119 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
123 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
125 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
129 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
131 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
138 /* Set ECSPI1 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
140 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
145 /* Set ECSPI2 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
147 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()
152 /* Set ECSPI3 source to SYSTEM PLL1 800MHZ */ in SOC_ClockInit()
154 /* Set root clock to 800MHZ / 10 = 80MHZ */ in SOC_ClockInit()