Lines Matching full:mhz
20 * HFXOSC (16 MHz) is used to produce coreclk (and therefore tlclk / in soc_early_init_hook()
22 * - 16 MHz (bypass HFPLL). in soc_early_init_hook()
23 * - 48 MHz - 320 MHz, in 8 MHz steps (use HFPLL). in soc_early_init_hook()
25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
36 /* refr = 8 MHz. */ in soc_early_init_hook()
40 /* Select Q divisor to produce vco on [384 MHz, 768 MHz]. */ in soc_early_init_hook()
41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()
43 } else if (MHZ(768) / 4 >= CORECLK_HZ) { in soc_early_init_hook()
49 const int pll_f = ((CORECLK_HZ / MHZ(1)) >> (4 - pll_q)) - 1; in soc_early_init_hook()