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/Zephyr-latest/boards/raytac/mdbt53_db_40/
Draytac_mdbt53_db_40_nrf5340_cpunet_common.dts40 boot_partition: partition@0 {
42 reg = <0x00000000 0xc000>;
45 label = "image-0";
46 reg = <0x0000C000 0x17000>;
50 reg = <0x00023000 0x17000>;
54 reg = <0x0003a000 0x6000>;
/Zephyr-latest/boards/raytac/mdbt53v_db_40/
Draytac_mdbt53v_db_40_nrf5340_cpunet_common.dts40 boot_partition: partition@0 {
42 reg = <0x00000000 0xc000>;
45 label = "image-0";
46 reg = <0x0000C000 0x17000>;
50 reg = <0x00023000 0x17000>;
54 reg = <0x0003a000 0x6000>;
/Zephyr-latest/drivers/ipm/
DKconfig.intel_adsp24 default 0x6000
34 default 0x1000
37 within the pre-existing window 0 (this is not the same as
/Zephyr-latest/dts/bindings/mtd/
Dnordic,owned-partitions.yaml22 reg = <0xe000000 0x200000>;
32 label = "image-0";
33 reg = <0xc0000 0x40000>;
45 reg = <0x100000 0x50000>;
49 reg = <0x150000 0x6000>;
56 - 0x0E0C0000--0x0E100000, with read & execute permissions, containing the
57 partition labeled "image-0".
58 - 0x0E100000--0x0E156000, with read & write permissions, containing the
/Zephyr-latest/boards/nordic/nrf5340_audio_dk/
Dnrf5340_audio_dk_nrf5340_cpunet.dts35 pinctrl-0 = <&spi0_default>;
55 pinctrl-0 = <&uart0_default>;
67 boot_partition: partition@0 {
69 reg = <0x00000000 0xc000>;
72 label = "image-0";
73 reg = <0x0000C000 0x12000>;
77 reg = <0x0001E000 0x12000>;
81 reg = <0x0003a000 0x6000>;
/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dfir_q15.pat2 0xFFC6, 0x0251, 0x0376, 0x02B3, 0x0158, 0xFE63, 0xFCC4, 0xFC4D,
3 0xFD55, 0xFFED, 0x02A3, 0x036D, 0x033E, 0x0147, 0xFE71, 0xFC4E,
4 0xFC67, 0xFD5E, 0xFF34, 0x02D8, 0x0340, 0x0362, 0x0147, 0xFED7,
5 0xFCBD, 0xFBF9, 0xFDE3, 0x0039, 0x026F, 0x035C, 0x035E, 0x019A,
6 0xFEE8, 0xFCA6, 0xFC4C, 0xFDB7, 0xFFBC, 0x0214, 0x0371, 0x02F5,
7 0x0187, 0xFE46, 0xFC4E, 0xFBBC, 0xFE67, 0xFFC6
11 0x4000, 0x2000, 0x0000, 0x4CCD, 0x3333, 0x199A, 0x5555, 0x4000,
12 0x2AAB, 0x1555, 0x0000, 0x5B6E, 0x4925, 0x36DB, 0x2492, 0x1249,
13 0x6000, 0x5000, 0x4000, 0x3000, 0x2000, 0x1000, 0x0000, 0x638E,
14 0x5555, 0x471C, 0x38E4, 0x2AAB, 0x1C72, 0x0E39, 0x6666, 0x599A,
[all …]
/Zephyr-latest/boards/nordic/nrf5340dk/
Dnrf5340dk_nrf5340_cpunet.dts52 pinctrl-0 = <&uart0_default>;
63 pinctrl-0 = <&i2c0_default>;
73 pinctrl-0 = <&spi0_default>;
85 boot_partition: partition@0 {
87 reg = <0x00000000 0xc000>;
90 label = "image-0";
91 reg = <0x0000C000 0x17000>;
95 reg = <0x00023000 0x17000>;
99 reg = <0x0003a000 0x6000>;
/Zephyr-latest/soc/arm/beetle/
Dsoc.h33 #define _BEETLE_GPIO0 (1 << 0)
39 #define _BEETLE_TIMER0 (1 << 0)
57 #define _BEETLE_APB_BASE 0x40000000
58 #define _BEETLE_APB_PER_SIZE 0x1000
59 #define _BEETLE_APB_FULL_SIZE 0x10000
60 #define _BEETLE_AHB_BASE 0x40010000
61 #define _BEETLE_AHB_PER_SIZE 0x1000
62 #define _BEETLE_AHB_FULL_SIZE 0x10000
65 #define _BEETLE_GPIO0_BASE (_BEETLE_AHB_BASE + 0x0000)
66 #define _BEETLE_GPIO1_BASE (_BEETLE_AHB_BASE + 0x1000)
[all …]
/Zephyr-latest/subsys/fs/ext2/
Dext2.h11 #define EXT2_MAGIC_NUMBER 0xEF53
17 #define EXT2_FEATURE_INCOMPAT_COMPRESSION 0x0001 /* Disk/File compression is used */
18 #define EXT2_FEATURE_INCOMPAT_FILETYPE 0x0002 /* Directory entries record the file type */
19 #define EXT3_FEATURE_INCOMPAT_RECOVER 0x0004 /* Filesystem needs recovery */
20 #define EXT3_FEATURE_INCOMPAT_JOURNAL_DEV 0x0008 /* Filesystem has a separate journal device */
21 #define EXT2_FEATURE_INCOMPAT_META_BG 0x0010 /* Meta block groups */
25 #define EXT2_FEATURE_RO_COMPAT_SPARSE_SUPER 0x0001 /* Sparse Superblock */
26 #define EXT2_FEATURE_RO_COMPAT_LARGE_FILE 0x0002 /* Large file support, 64-bit file size */
27 #define EXT2_FEATURE_RO_COMPAT_BTREE_DIR 0x0004 /* Binary tree sorted directory files */
29 #define EXT2_FEATURE_RO_COMPAT_SUPPORTED (0)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Dadsp_memory.h18 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
43 #define IMR_BOOT_LDR_DATA_BASE 0xB0039000
44 #define IMR_BOOT_LDR_MANIFEST_BASE 0xB0032000
45 #define IMR_BOOT_LDR_TEXT_ENTRY_BASE (IMR_BOOT_LDR_MANIFEST_BASE + 0x6000)
47 #define ADSP_L1_CACHE_PREFCTL_VALUE 0x1038
50 #define ADSP_L1CC_ADDR (0x9F080080)
51 #define ADSP_CxL1CCAP_ADDR (ADSP_L1CC_ADDR + 0x0000)
52 #define ADSP_CxL1CCFG_ADDR (ADSP_L1CC_ADDR + 0x0004)
53 #define ADSP_CxL1PCFG_ADDR (ADSP_L1CC_ADDR + 0x0008)
/Zephyr-latest/doc/connectivity/networking/api/
Dptp.rst67 0x0000, NULL_PTP_MANAGEMENT, GET SET COMMAND
68 0x0001, CLOCK_DESCRIPTION, GET
69 0x0002, USER_DESCRIPTION, GET
70 0x0003, SAVE_IN_NON_VOLATILE_STORAGE, -
71 0x0004, RESET_NON_VOLATILE_STORAGE, -
72 0x0005, INITIALIZE, -
73 0x0006, FAULT_LOG, -
74 0x0007, FAULT_LOG_RESET, -
75 0x2000, DEFAULT_DATA_SET, GET
76 0x2001, CURRENT_DATA_SET, GET
[all …]
/Zephyr-latest/soc/amd/acp_6_0/adsp/
Dmemory.h12 #define PLATFORM_PRIMARY_CORE_ID 0
14 #define IRAM_BASE 0x7F000000
15 #define IRAM_SIZE 0x60000
17 #define IRAM_RESERVE_HEADER_SPACE 0x400
19 #define MEM_RESET_TEXT_SIZE 0x400
20 #define MEM_RESET_LIT_SIZE 0x8
21 #define XCHAL_RESET_VECTOR_PADDR_IRAM 0x7F000000
22 #define XCHAL_WINDOW_VECTORS_PADDR_IRAM 0x7F000400
26 #define MEM_VECBASE_LIT_SIZE 0x178
27 #define MEM_WIN_TEXT_SIZE 0x178
[all …]
/Zephyr-latest/boards/panasonic/pan1781_evb/
Dpan1781_evb.dts43 pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
64 gpio-map-mask = <0xffffffff 0xffffffc0>;
65 gpio-map-pass-thru = <0 0x3f>;
66 gpio-map = <0 0 &gpio0 2 0>, /* A0 */
67 <1 0 &gpio0 3 0>, /* A1 */
68 <2 0 &gpio0 4 0>, /* A2 */
69 <3 0 &gpio0 5 0>, /* A3 */
70 <6 0 &gpio0 6 0>, /* D0 */
71 <7 0 &gpio0 8 0>, /* D1 */
72 <8 0 &gpio0 14 0>, /* D2 */
[all …]
/Zephyr-latest/boards/nordic/nrf7002dk/
Dnrf7002dk_nrf5340_cpunet.dts34 label = "Green LED 0";
59 gpio-map-mask = <0xffffffff 0xffffffc0>;
60 gpio-map-pass-thru = <0 0x3f>;
61 gpio-map = <0 0 &gpio0 4 0>, /* A0 */
62 <1 0 &gpio0 5 0>, /* A1 */
63 <2 0 &gpio0 6 0>, /* A2 */
64 <3 0 &gpio0 7 0>, /* A3 */
65 <4 0 &gpio0 25 0>, /* A4 */
66 <5 0 &gpio0 26 0>, /* A5 */
67 <6 0 &gpio1 0 0>, /* D0 */
[all …]
/Zephyr-latest/boards/nordic/thingy53/
Dthingy53_nrf5340_cpunet.dts73 gpio-map-mask = <0xffffffff 0xffffffc0>;
74 gpio-map-pass-thru = <0 0x3f>;
75 gpio-map = <5 0 &gpio1 1 0>, /* P5, P1.01/GRANT */
76 <6 0 &gpio1 0 0>, /* P6, P1.00/REQ */
77 <8 0 &gpio0 5 0>, /* P8, P0.05/AIN1 */
78 <9 0 &gpio0 4 0>, /* P9, P0.04/AIN0 */
79 <15 0 &gpio0 8 0>, /* P15, P0.08/TRACEDATA3 */
80 <16 0 &gpio0 9 0>, /* P16, P0.09/TRACEDATA2 */
81 <17 0 &gpio0 10 0>, /* P17, P0.10/TRACEDATA1 */
82 <18 0 &gpio0 11 0>, /* P18, P0.11/TRACEDATA0 */
[all …]
/Zephyr-latest/boards/raytac/mdbt50q_db_33/
Draytac_mdbt50q_db_33_nrf52833.dts32 label = "Green LED 0";
47 pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
55 label = "Push button switch 0";
120 pinctrl-0 = <&uart0_default>;
129 pinctrl-0 = <&uart1_default>;
137 pinctrl-0 = <&i2c0_default>;
146 pinctrl-0 = <&i2c1_default>;
153 pinctrl-0 = <&pwm0_default>;
162 pinctrl-0 = <&spi0_default>;
170 pinctrl-0 = <&spi1_default>;
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Dadsp_memory.h24 #define ROM_JUMP_ADDR (LP_SRAM_BASE + 0x10)
45 #define IMR_BOOT_LDR_MANIFEST_OFFSET 0x42000
46 #define IMR_BOOT_LDR_MANIFEST_SIZE 0x6000
49 #define IMR_BOOT_LDR_TEXT_ENTRY_SIZE 0x180
52 #define IMR_BOOT_LDR_LIT_SIZE 0x40
56 #define IMR_BOOT_LDR_TEXT_SIZE 0x1C00
59 #define IMR_BOOT_LDR_DATA_OFFSET 0x49000
61 #define IMR_BOOT_LDR_DATA_SIZE 0xA8000
63 #define IMR_BOOT_LDR_BSS_OFFSET 0x110000
65 #define IMR_BOOT_LDR_BSS_SIZE 0x40000
[all …]
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
Dmemory.h9 #define IRAM_RESERVE_HEADER_SPACE 0x400
11 #define IRAM_BASE 0x21170000
12 #define IRAM_SIZE 0x10000
14 #define SDRAM0_BASE 0x1a000000
15 #define SDRAM0_SIZE 0x800000
17 #define SDRAM1_BASE 0x1a800000
18 #define SDRAM1_SIZE 0x800000
21 #define MEM_RESET_TEXT_SIZE 0x2e0
22 #define MEM_RESET_LIT_SIZE 0x120
28 #define MEM_VECBASE_LIT_SIZE 0x178
[all …]
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/
Dmemory.h10 #define IRAM_RESERVE_HEADER_SPACE 0x400
12 #define IRAM_BASE 0x596f8000
13 #define IRAM_SIZE 0x800
15 #define SDRAM0_BASE 0x92400000
16 #define SDRAM0_SIZE 0x800000
18 #define SDRAM1_BASE 0x92C00000
19 #define SDRAM1_SIZE 0x800000
22 #define MEM_RESET_TEXT_SIZE 0x2e0
23 #define MEM_RESET_LIT_SIZE 0x120
29 #define MEM_VECBASE_LIT_SIZE 0x178
[all …]
/Zephyr-latest/soc/nxp/imx/imx8/adsp/
Dmemory.h10 #define IRAM_RESERVE_HEADER_SPACE 0x400
12 #define IRAM_BASE 0x596f8000
13 #define IRAM_SIZE 0x800
15 #define SDRAM0_BASE 0x92400000
16 #define SDRAM0_SIZE 0x800000
18 #define SDRAM1_BASE 0x92C00000
19 #define SDRAM1_SIZE 0x800000
22 #define MEM_RESET_TEXT_SIZE 0x2e0
23 #define MEM_RESET_LIT_SIZE 0x120
29 #define MEM_VECBASE_LIT_SIZE 0x178
[all …]
/Zephyr-latest/boards/panasonic/pan1783/
Dpan1783_nrf5340_cpunet_common.dtsi69 gpio-map-mask = <0xffffffff 0xffffffc0>;
70 gpio-map-pass-thru = <0 0x3f>;
71 gpio-map = <0 0 &gpio0 4 0>, /* AN */
73 <2 0 &gpio1 12 0>, /* CS */
74 <3 0 &gpio1 15 0>, /* SCK */
75 <4 0 &gpio1 14 0>, /* MISO */
76 <5 0 &gpio1 13 0>, /* MOSI */
79 <6 0 &gpio1 7 0>, /* PWM */
80 <7 0 &gpio1 4 0>, /* INT */
81 <8 0 &gpio1 0 0>, /* RX */
[all …]
/Zephyr-latest/boards/nordic/nrf9280pdk/
Dnrf9280pdk_nrf9280-memory_map.dtsi16 reg = <0x2f011000 DT_SIZE_K(4)>;
21 ranges = <0x0 0x2f011000 0x1000>;
23 cpusec_cpurad_ipc_shm: memory@0 {
24 reg = <0x0 DT_SIZE_K(2)>;
28 reg = <0x800 DT_SIZE_K(2)>;
34 reg = <0x2f012000 DT_SIZE_K(516)>;
39 ranges = <0x0 0x2f012000 0x81000>;
41 cpusec_cpuapp_ipc_shm: memory@0 {
42 reg = <0x0 DT_SIZE_K(2)>;
46 reg = <0x800 DT_SIZE_K(2)>;
[all …]
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
Dmemory.h13 #define PLATFORM_PRIMARY_CORE_ID 0
15 #define IRAM_RESERVE_HEADER_SPACE 0x400
17 #define IRAM_BASE 0x3B6F8000
18 #define IRAM_SIZE 0x800
20 #define SDRAM0_BASE 0x92400000
21 #define SDRAM0_SIZE 0x800000
23 #define SDRAM1_BASE 0x92C00000
24 #define SDRAM1_SIZE 0x800000
27 #define MEM_RESET_TEXT_SIZE 0x2E0
28 #define MEM_RESET_LIT_SIZE 0x120
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/fastmath/src/
Dq15.pat2 0x0000, 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7FFF,
3 0xF000, 0xE000, 0xD000, 0xC000, 0xB000, 0xA000, 0x8000, 0x0000,
4 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7FFF
8 0xCCCD, 0x0000, 0x0CCD, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF
12 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
13 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
14 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
15 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
16 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
17 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD, 0x8CCD,
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3_priv.h15 #define GIC_BASER_CACHE_NGNRNE 0x0UL /* Device-nGnRnE */
16 #define GIC_BASER_CACHE_INNERLIKE 0x0UL /* Same as Inner Cacheability. */
17 #define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */
18 #define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */
19 #define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */
20 #define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */
21 #define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */
22 #define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */
23 #define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */
24 #define GIC_BASER_SHARE_NO 0x0UL /* Non-shareable */
[all …]

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