Lines Matching +full:0 +full:x6000

9 #define IRAM_RESERVE_HEADER_SPACE	0x400
11 #define IRAM_BASE	0x21170000
12 #define IRAM_SIZE	0x10000
14 #define SDRAM0_BASE	0x1a000000
15 #define SDRAM0_SIZE	0x800000
17 #define SDRAM1_BASE	0x1a800000
18 #define SDRAM1_SIZE	0x800000
21 #define MEM_RESET_TEXT_SIZE			0x2e0
22 #define MEM_RESET_LIT_SIZE			0x120
28 #define MEM_VECBASE_LIT_SIZE			0x178
33 #define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x21170000
36 #define MEM_VECT_LIT_SIZE			0x4
37 #define MEM_VECT_TEXT_SIZE			0x1C
45 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
48 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
51 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
54 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
57 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
60 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
63 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
72 #define IDT_SIZE	0x2000
75 #define IRAM_BASE	0x21170000
76 #define IRAM_SIZE	0x10000
78 #define DRAM0_BASE	0x21180000
79 #define DRAM0_SIZE	0x10000
81 #define SDRAM0_BASE	0x1a000000
82 #define SDRAM0_SIZE	0x800000
84 #define SDRAM1_BASE	0x1a800000
85 #define SDRAM1_SIZE	0x800000
87 #define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x2DA20000
90 #define EDMA2_BASE	0x2D810000
91 #define EDMA2_SIZE	0x10000
93 #define SAI_5_BASE	0x29890000
94 #define SAI_5_SIZE	0x00010000
95 #define SAI_6_BASE	0x2DA90000
96 #define SAI_6_SIZE	0x00010000
97 #define SAI_7_BASE	0x2DAA0000
98 #define SAI_7_SIZE	0x00010000
100 #define UUID_ENTRY_ELF_BASE	0x1FFFA000
101 #define UUID_ENTRY_ELF_SIZE	0x6000
103 #define LOG_ENTRY_ELF_BASE	0x20000000
104 #define LOG_ENTRY_ELF_SIZE	0x2000000
107 #define EXT_MANIFEST_ELF_SIZE	0x2000000
132 #define SRAM_OUTBOX_SIZE	0x1000
133 #define SRAM_OUTBOX_OFFSET	0
136 #define SRAM_INBOX_SIZE		0x1000
140 #define SRAM_DEBUG_SIZE		0x2800
144 #define SRAM_EXCEPT_SIZE	0x800
148 #define SRAM_STREAM_SIZE	0x1000
152 #define SRAM_TRACE_SIZE		0x1000