Lines Matching +full:0 +full:x6000

13 #define PLATFORM_PRIMARY_CORE_ID	0
15 #define IRAM_RESERVE_HEADER_SPACE	0x400
17 #define IRAM_BASE	0x3B6F8000
18 #define IRAM_SIZE	0x800
20 #define SDRAM0_BASE	0x92400000
21 #define SDRAM0_SIZE	0x800000
23 #define SDRAM1_BASE	0x92C00000
24 #define SDRAM1_SIZE	0x800000
27 #define MEM_RESET_TEXT_SIZE			0x2E0
28 #define MEM_RESET_LIT_SIZE			0x120
34 #define MEM_VECBASE_LIT_SIZE			0x178
39 #define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x3B6F8000
42 #define MEM_VECT_LIT_SIZE			0x4
43 #define MEM_VECT_TEXT_SIZE			0x1C
51 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
54 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
57 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
60 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
63 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
66 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
69 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
78 #define IDT_SIZE	0x2000
81 #define IRAM_BASE	0x3B6F8000
82 #define IRAM_SIZE	0x800
84 #define DRAM0_BASE	0x3B6E8000
85 #define DRAM0_SIZE	0x8000
87 #define DRAM1_BASE	0x3B6F0000
88 #define DRAM1_SIZE	0x8000
90 #define SDRAM0_BASE	0x92400000
91 #define SDRAM0_SIZE	0x800000
93 #define SDRAM1_BASE	0x92C00000
94 #define SDRAM1_SIZE	0x800000
96 #define XSHAL_MU2_SIDEB_BYPASS_PADDR 0x30E70000
99 #define SDMA2_BASE	0x30E10000
100 #define SDMA2_SIZE	0x10000
102 #define SDMA3_BASE	0x30E00000
103 #define SDMA3_SIZE	0x10000
105 #define SAI_1_BASE	0x30C10000
106 #define SAI_1_SIZE	0x00010000
108 #define SAI_3_BASE	0x30C30000
109 #define SAI_3_SIZE	0x00010000
110 #define UUID_ENTRY_ELF_BASE	0x1FFFA000
111 #define UUID_ENTRY_ELF_SIZE	0x6000
113 #define LOG_ENTRY_ELF_BASE	0x20000000
114 #define LOG_ENTRY_ELF_SIZE	0x2000000
117 #define EXT_MANIFEST_ELF_SIZE	0x2000000
142 #define SRAM_OUTBOX_SIZE	0x1000
143 #define SRAM_OUTBOX_OFFSET	0
146 #define SRAM_INBOX_SIZE		0x1000
150 #define SRAM_DEBUG_SIZE		0x800
154 #define SRAM_EXCEPT_SIZE	0x800
158 #define SRAM_STREAM_SIZE	0x1000
162 #define SRAM_TRACE_SIZE		0x1000