1 /* 2 * Copyright (c) 2021 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ 8 #define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ 9 10 #define IRAM_RESERVE_HEADER_SPACE 0x400 11 12 #define IRAM_BASE 0x596f8000 13 #define IRAM_SIZE 0x800 14 15 #define SDRAM0_BASE 0x92400000 16 #define SDRAM0_SIZE 0x800000 17 18 #define SDRAM1_BASE 0x92C00000 19 #define SDRAM1_SIZE 0x800000 20 21 /* The reset vector address in SRAM and its size */ 22 #define MEM_RESET_TEXT_SIZE 0x2e0 23 #define MEM_RESET_LIT_SIZE 0x120 24 25 /* This is the base address of all the vectors defined in IRAM */ 26 #define XCHAL_VECBASE_RESET_PADDR_IRAM \ 27 (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE) 28 29 #define MEM_VECBASE_LIT_SIZE 0x178 30 31 /* 32 * EXCEPTIONS and VECTORS 33 */ 34 #define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x596F8000 35 36 /* Vector and literal sizes */ 37 #define MEM_VECT_LIT_SIZE 0x4 38 #define MEM_VECT_TEXT_SIZE 0x1C 39 #define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ 40 MEM_VECT_LIT_SIZE) 41 42 /* The addresses of the vectors. 43 * Only the mem_error vector continues to point to its ROM address. 44 */ 45 #define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \ 46 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C) 47 48 #define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \ 49 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C) 50 51 #define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \ 52 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC) 53 54 #define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \ 55 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC) 56 57 #define XCHAL_KERNEL_VECTOR_PADDR_IRAM \ 58 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC) 59 60 #define XCHAL_USER_VECTOR_PADDR_IRAM \ 61 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C) 62 63 #define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \ 64 (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C) 65 66 /* Location for the intList section which is later used to construct the 67 * Interrupt Descriptor Table (IDT). This is a bogus address as this 68 * section will be stripped off in the final image. 69 */ 70 #define IDT_BASE (IRAM_BASE + IRAM_SIZE) 71 72 /* size of the Interrupt Descriptor Table (IDT) */ 73 #define IDT_SIZE 0x2000 74 75 /* physical DSP addresses */ 76 #define IRAM_BASE 0x596f8000 77 #define IRAM_SIZE 0x800 78 79 #define DRAM0_BASE 0x596e8000 80 #define DRAM0_SIZE 0x8000 81 82 #define DRAM1_BASE 0x596f0000 83 #define DRAM1_SIZE 0x8000 84 85 #define SDRAM0_BASE 0x92400000 86 #define SDRAM0_SIZE 0x800000 87 88 #define SDRAM1_BASE 0x92C00000 89 #define SDRAM1_SIZE 0x800000 90 91 #define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000 92 #define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR 93 94 #define EDMA0_BASE 0x59200000 95 #define EDMA0_SIZE 0x10000 96 97 #define ESAI_BASE 0x59010000 98 #define ESAI_SIZE 0x00010000 99 100 #define SAI_1_BASE 0x59050000 101 #define SAI_1_SIZE 0x00010000 102 103 #define UUID_ENTRY_ELF_BASE 0x1FFFA000 104 #define UUID_ENTRY_ELF_SIZE 0x6000 105 106 #define LOG_ENTRY_ELF_BASE 0x20000000 107 #define LOG_ENTRY_ELF_SIZE 0x2000000 108 109 #define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) 110 #define EXT_MANIFEST_ELF_SIZE 0x2000000 111 112 /* 113 * The Heap and Stack on i.MX8 are organized like this :- 114 * 115 * +--------------------------------------------------------------------------+ 116 * | Offset | Region | Size | 117 * +---------------------+----------------+-----------------------------------+ 118 * | SDRAM_BASE | RO Data | SOF_DATA_SIZE | 119 * | | Data | | 120 * | | BSS | | 121 * +---------------------+----------------+-----------------------------------+ 122 * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | 123 * +---------------------+----------------+-----------------------------------+ 124 * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | 125 * +---------------------+----------------+-----------------------------------+ 126 * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | 127 * +---------------------+----------------+-----------------------------------+ 128 * | SOF_STACK_END | Stack | SOF_STACK_SIZE | 129 * +---------------------+----------------+-----------------------------------+ 130 * | SOF_STACK_BASE | | | 131 * +---------------------+----------------+-----------------------------------+ 132 */ 133 134 #define SRAM_OUTBOX_BASE SDRAM1_BASE 135 #define SRAM_OUTBOX_SIZE 0x1000 136 #define SRAM_OUTBOX_OFFSET 0 137 138 #define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) 139 #define SRAM_INBOX_SIZE 0x1000 140 #define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE 141 142 #define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) 143 #define SRAM_DEBUG_SIZE 0x800 144 #define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) 145 146 #define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) 147 #define SRAM_EXCEPT_SIZE 0x800 148 #define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) 149 150 #define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) 151 #define SRAM_STREAM_SIZE 0x1000 152 #define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) 153 154 #define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) 155 #define SRAM_TRACE_SIZE 0x1000 156 #define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) 157 158 #define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \ 159 + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \ 160 + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) 161 162 #endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */ 163