Lines Matching +full:0 +full:x6000

10 #define IRAM_RESERVE_HEADER_SPACE	0x400
12 #define IRAM_BASE	0x596f8000
13 #define IRAM_SIZE	0x800
15 #define SDRAM0_BASE	0x92400000
16 #define SDRAM0_SIZE	0x800000
18 #define SDRAM1_BASE	0x92C00000
19 #define SDRAM1_SIZE	0x800000
22 #define MEM_RESET_TEXT_SIZE			0x2e0
23 #define MEM_RESET_LIT_SIZE			0x120
29 #define MEM_VECBASE_LIT_SIZE			0x178
34 #define XCHAL_RESET_VECTOR0_PADDR_IRAM	0x596F8000
37 #define MEM_VECT_LIT_SIZE			0x4
38 #define MEM_VECT_TEXT_SIZE			0x1C
46 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C)
49 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C)
52 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC)
55 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC)
58 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC)
61 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C)
64 	(XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C)
73 #define IDT_SIZE	0x2000
76 #define IRAM_BASE	0x596f8000
77 #define IRAM_SIZE	0x800
79 #define DRAM0_BASE	0x596e8000
80 #define DRAM0_SIZE	0x8000
82 #define DRAM1_BASE	0x596f0000
83 #define DRAM1_SIZE	0x8000
85 #define SDRAM0_BASE	0x92400000
86 #define SDRAM0_SIZE	0x800000
88 #define SDRAM1_BASE	0x92C00000
89 #define SDRAM1_SIZE	0x800000
91 #define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000
94 #define EDMA0_BASE	0x59200000
95 #define EDMA0_SIZE	0x10000
97 #define ESAI_BASE	0x59010000
98 #define ESAI_SIZE	0x00010000
100 #define SAI_1_BASE	0x59050000
101 #define SAI_1_SIZE	0x00010000
103 #define UUID_ENTRY_ELF_BASE	0x1FFFA000
104 #define UUID_ENTRY_ELF_SIZE	0x6000
106 #define LOG_ENTRY_ELF_BASE	0x20000000
107 #define LOG_ENTRY_ELF_SIZE	0x2000000
110 #define EXT_MANIFEST_ELF_SIZE	0x2000000
135 #define SRAM_OUTBOX_SIZE	0x1000
136 #define SRAM_OUTBOX_OFFSET	0
139 #define SRAM_INBOX_SIZE		0x1000
143 #define SRAM_DEBUG_SIZE		0x800
147 #define SRAM_EXCEPT_SIZE	0x800
151 #define SRAM_STREAM_SIZE	0x1000
155 #define SRAM_TRACE_SIZE		0x1000