Lines Matching +full:0 +full:x6000
16 reg = <0x2f011000 DT_SIZE_K(4)>;
21 ranges = <0x0 0x2f011000 0x1000>;
23 cpusec_cpurad_ipc_shm: memory@0 {
24 reg = <0x0 DT_SIZE_K(2)>;
28 reg = <0x800 DT_SIZE_K(2)>;
34 reg = <0x2f012000 DT_SIZE_K(516)>;
39 ranges = <0x0 0x2f012000 0x81000>;
41 cpusec_cpuapp_ipc_shm: memory@0 {
42 reg = <0x0 DT_SIZE_K(2)>;
46 reg = <0x800 DT_SIZE_K(2)>;
50 reg = <0x1000 DT_SIZE_K(512)>;
56 reg = <0x2f0cf000 DT_SIZE_K(4)>;
62 ranges = <0x0 0x2f0cf000 0x1000>;
64 cpuapp_cpurad_ipc_shm: memory@0 {
65 reg = <0x0 DT_SIZE_K(2)>;
69 reg = <0x800 DT_SIZE_K(2)>;
75 reg = <0x2f0d0000 DT_SIZE_K(36)>;
81 ranges = <0x0 0x2f0d0000 0x9000>;
86 cpuapp_cpucell_ipc_shm_ctrl: memory@0 {
87 reg = <0x0 0x1000>;
92 reg = <0x1000 0x4000>;
97 reg = <0x5000 0x4000>;
102 reg = <0x2f88fce0 0x80>;
106 reg = <0x2f88fd60 0x80>;
110 reg = <0x2f88fe00 0x80>;
114 reg = <0x2f88fe80 0x80>;
120 reg = <0x2f890000 DT_SIZE_K(32)>;
124 ranges = <0x0 0x2f890000 0x8000>;
128 reg = <0x4000 DT_SIZE_K(16)>;
130 #memory-region-cells = <0>;
138 reg = <0x2fc00000 DT_SIZE_K(24)>;
143 ranges = <0x0 0x2fc00000 0x6000>;
145 cpuppr_code_data: memory@0 {
146 reg = <0x0 DT_SIZE_K(22)>;
150 reg = <0x5800 DT_SIZE_K(1)>;
154 reg = <0x5c00 DT_SIZE_K(1)>;
160 reg = <0x2fc06000 DT_SIZE_K(4)>;
162 #memory-region-cells = <0>;
170 reg = <0x2fc07000 DT_SIZE_K(1)>;
172 #memory-region-cells = <0>;
189 reg = <0x402000 DT_SIZE_K(256)>;
201 reg = <0x442000 DT_SIZE_K(1024)>;
205 reg = <0x542000 DT_SIZE_K(64)>;
217 reg = <0x600000 DT_SIZE_K(512)>;
221 reg = <0x680000 DT_SIZE_K(24)>;