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/Zephyr-latest/boards/renode/riscv32_virtual/support/
Driscv32_virtual.repl4 flash: Memory.MappedMemory @ sysbus 0x80000000
5 size: 0x400000
7 ddr: Memory.MappedMemory @ sysbus 0x80400000
8 size: 0x400000
10 uart0: UART.NS16550 @ sysbus 0x10000000
13 uart1: UART.NS16550 @ sysbus 0x10000100
21 plic0: IRQControllers.PlatformLevelInterruptController @ sysbus 0x0C000000
22 0 -> cpu@11
26 plic1: IRQControllers.PlatformLevelInterruptController @ sysbus 0x08000000
27 0 -> cpu@4
[all …]
/Zephyr-latest/boards/qemu/x86/
DKconfig.defconfig30 default 0x10000000 if ACPI
53 default 0x10000000 if ACPI
61 default 0x400000
83 default 0x400000
111 default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0)
Dqemu_x86_tiny_defconfig21 CONFIG_KERNEL_VM_SIZE=0x400000
22 CONFIG_KERNEL_VM_BASE=0x40000000
23 CONFIG_KERNEL_VM_OFFSET=0x100000
24 CONFIG_SRAM_OFFSET=0
Dqemu_x86_atom_virt_defconfig16 CONFIG_SRAM_OFFSET=0x100000
17 CONFIG_KERNEL_VM_SIZE=0x400000
18 CONFIG_KERNEL_VM_BASE=0x40000000
19 CONFIG_KERNEL_VM_OFFSET=0
/Zephyr-latest/soc/intel/intel_socfpga/agilex5/
DKconfig.defconfig.agilex515 default 0x400000
/Zephyr-latest/dts/nios2/intel/
Dnios2-qemu.dtsi8 #size-cells = <0>;
10 cpu: cpu@0 {
13 reg = <0>;
21 reg = <0x420000 0x20000>;
26 reg = <0x400000 0x20000>;
38 reg = <0x201000 0x400>;
39 interrupts = <0>;
45 reg = <0x440000 0x400>;
Dnios2f.dtsi9 #size-cells = <0>;
11 cpu: cpu@0 {
14 reg = <0>;
20 flash0: flash@0 {
22 reg = <0x00 0xb8000>;
27 reg = <0x400000 0x20000>;
39 reg = <0x100000 0x400>;
41 interrupts = <1 0>;
48 reg = <0x201000 0x8>;
57 #size-cells = <0>;
[all …]
/Zephyr-latest/dts/arm64/broadcom/
Dbcm2712.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
43 reg = <0x0 0x200000 0x80000>;
48 reg = <0x10 0x7fff9000 0x1000>,
49 <0x10 0x7fffa000 0x2000>;
57 reg = <0x10 0x7d517c00 0x40>;
60 #size-cells = <0>;
61 gio_aon: gpio@0 {
63 reg = <0>;
[all …]
/Zephyr-latest/soc/espressif/esp32s2/
Dmemory.h18 * - 0x3ffeab00 - 0x3fffc410: Shared buffers, used in UART/USB/SPI download mode only
19 * - 0x3fffc410 - 0x3fffe710: CPU stack, can be reclaimed as heap after RTOS startup
20 * - 0x3fffe710 - 0x40000000: ROM .bss and .data (not easily reclaimable)
23 * buffers area (0x3fffc410). For alignment purpose we shall use value (0x3fce9700).
27 * Used to convert between 0x4002xxxx and 0x3ffbxxxx addresses.
29 #define IRAM_DRAM_OFFSET 0x70000
30 #define DRAM_BUFFERS_START 0x3ffea400
31 #define DRAM_BUFFERS_END 0x3fffc410
32 #define DRAM_ROM_CPU_STACK_START 0x3fffc410
33 #define DRAM_ROM_BSS_DATA_START 0x3fffe710
[all …]
/Zephyr-latest/soc/espressif/esp32c2/
Dmemory.h23 * - 0x3fccb264 - 0x3fcdcb70: Shared buffers, used in UART/USB/SPI download mode only
24 * - 0x3fcdcb70 - 0x3fcdeb70: PRO CPU stack, can be reclaimed as heap after RTOS startup
25 * - 0x3fcdeb70 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
28 * buffers area (0x3fcdcb70).
32 * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
34 #define IRAM_DRAM_OFFSET 0x6e0000
36 #define DRAM_BUFFERS_START 0x3fccb264
37 #define DRAM_STACK_START 0x3fcdcb70
38 #define DRAM_ROM_BSS_DATA_START 0x3fcdeb70
43 #define BOOTLOADER_STACK_OVERHEAD 0x0
[all …]
/Zephyr-latest/soc/espressif/esp32c6/
Dmemory.h16 #define ICACHE_SIZE 0x8000
22 * - 0x4086ad08 - 0x4087c610: Shared buffers, used in UART/USB/SPI download mode only
23 * - 0x4087c610 - 0x4087e610: PRO CPU stack, can be reclaimed as heap after RTOS startup
24 * - 0x4087e610 - 0x40880000: ROM .bss and .data (not easily reclaimable)
27 * buffers area (0x4087c610).
30 #define DRAM_BUFFERS_START 0x4086ad08
31 #define DRAM_BUFFERS_END 0x4087c610
33 #define DRAM_ROM_BSS_DATA_START 0x4087e610
39 #define BOOTLOADER_STACK_OVERHEAD 0x0
41 #define BOOTLOADER_DRAM_SEG_LEN 0xA000
[all …]
/Zephyr-latest/soc/espressif/esp32c3/
Dmemory.h21 * - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
22 * - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
23 * - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
26 * buffers area (0x3fcdc710).
30 * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
32 #define IRAM_DRAM_OFFSET 0x700000
33 #define DRAM_BUFFERS_START 0x3fccae00
34 #define DRAM_BUFFERS_END 0x3fccc000
35 #define DRAM_STACK_START 0x3fcdc710
36 #define DRAM_ROM_BSS_DATA_START 0x3fcde710
[all …]
/Zephyr-latest/boards/arm/mps2/
Dmps2_an385.dts33 gpios = <&gpio_led0 0>;
46 gpios = <&gpio_button 0>;
58 #size-cells = <0>;
60 cpu@0 {
62 reg = <0>;
68 reg = <0x20000000 0x400000>;
71 flash0: flash@0 {
73 reg = <0 0x400000>;
81 erase-value = <0x00>;
83 flash_sim0: flash_sim@0 {
[all …]
/Zephyr-latest/soc/altr/zephyr_nios2f/include/
Dlinker.h68 #define EXT_FLASH_AVL_MEM_REGION_BASE 0x8000000
70 #define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
72 #define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
74 #define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
76 #define RESET_REGION_BASE 0x0
Dsystem.h64 #define ALT_CPU_BIG_ENDIAN 0
65 #define ALT_CPU_BREAK_ADDR 0x00200820
69 #define ALT_CPU_CPU_ID_VALUE 0x00000000
71 #define ALT_CPU_DATA_ADDR_WIDTH 0x1c
72 #define ALT_CPU_DCACHE_BYPASS_MASK 0x80000000
76 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
77 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
78 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
83 #define ALT_CPU_HARDWARE_MULX_PRESENT 0
94 #define ALT_CPU_INST_ADDR_WIDTH 0x1c
[all …]
/Zephyr-latest/soc/altr/qemu_nios2/include/
Dlinker.h68 #define ONCHIP_FLASH_0_DATA_REGION_BASE 0x20
70 #define ONCHIP_MEMORY2_0_BEFORE_EXCEPTION_REGION_BASE 0x400000
72 #define ONCHIP_MEMORY2_0_REGION_BASE 0x400020
74 #define RESET_REGION_BASE 0x0
Dsystem.h53 #define ALT_CPU_BIG_ENDIAN 0
54 #define ALT_CPU_BREAK_ADDR 0x00200820
58 #define ALT_CPU_CPU_ID_VALUE 0x00000000
60 #define ALT_CPU_DATA_ADDR_WIDTH 0x17
61 #define ALT_CPU_DCACHE_LINE_SIZE 0
62 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
63 #define ALT_CPU_DCACHE_SIZE 0
64 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
65 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
66 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
[all …]
/Zephyr-latest/soc/espressif/esp32/
Dmemory.h9 #define SRAM0_CACHE_SIZE 0x10000
17 #define SRAM1_RESERVED_SIZE 0x8000
19 #define SRAM1_USER_SIZE (0x40000000 - SRAM1_DRAM_USER_START)
24 #define SRAM2_DRAM_SHM_SIZE 0x2000
33 * - 0x3ffae000 - 0x3ffb0000 (Reserved: data memory for ROM functions)
34 * - 0x3ffb0000 - 0x3ffe0000 (RAM bank 1 for application usage)
35 * - 0x3ffe0000 - 0x3ffe0440 (Reserved: data memory for ROM PRO CPU)
36 * - 0x3ffe3f20 - 0x3ffe4350 (Reserved: data memory for ROM APP CPU)
37 * - 0x3ffe4350 - 0x3ffe5230 (BT shm buffers)
38 * - 0x3ffe8000 - 0x3fffffff (RAM bank 2 for application usage)
[all …]
/Zephyr-latest/dts/bindings/mtd/
Datmel,sam-flash.yaml35 reg = <0x400e0a00 0x200>;
45 reg = <0x400000 0x100000>;
69 boot_partition: partition@0 {
71 reg = <0x0 0x10000>;
76 reg = <0x10000 0x70000>;
81 reg = <0x80000 0x70000>;
86 reg = <0xf0000 0x100000>;
/Zephyr-latest/tests/bluetooth/controller/common/include/
Dhelper_features.h13 #define FEAT_ENCODED 0x01
15 #define FEAT_ENCODED 0x00
19 #define FEAT_PARAM_REQ 0x02
21 #define FEAT_PARAM_REQ 0x00
25 #define FEAT_EXT_REJ 0x04
27 #define FEAT_EXT_REJ 0x00
31 #define FEAT_PERIPHERAL_FREQ 0x08
33 #define FEAT_PERIPHERAL_FREQ 0x00
37 #define FEAT_PING 0x10
39 #define FEAT_PING 0x00
[all …]
/Zephyr-latest/subsys/lorawan/services/
DKconfig40 according to LoRa Alliance TS003-2.0.0.
53 range from 128 (0x80) to 4194304 (0x400000).
64 according to TS004-1.0.0 as published by the LoRa Alliance.
164 TS005-1.0.0 as published by the LoRa Alliance.
/Zephyr-latest/boards/ezurio/rm1xx_dvk/
Drm1xx_dvk.dts55 pinctrl-0 = <&i2c0_default>;
65 pinctrl-0 = <&spi0_default>;
76 pinctrl-0 = <&spi1_default>;
79 at25: at25df041b@0 {
81 reg = <0>;
84 size = <0x400000>;
85 has-lock = <0xbc>;
111 pinctrl-0 = <&uart0_default>;
123 boot_partition: partition@0 {
125 reg = <0x00000000 0x0000C000>;
[all …]
/Zephyr-latest/doc/hardware/arch/
Dx86.rst61 are both ``0x0``.
63 - ``CONFIG_SRAM_BASE_ADDRESS == 0x00000000`` and
64 ``CONFIG_KERNEL_VM_BASE = 0x40000000`` is valid, while
66 - ``CONFIG_SRAM_BASE_ADDRESS == 0x00000000`` and
67 ``CONFIG_KERNEL_VM_BASE = 0x20000000`` is not.
91 --map 0xA0000000,0x2000
92 --map 0x80000000,0x400000,LWUX,0xB0000000)
/Zephyr-latest/arch/xtensa/core/
Dmmu.c13 BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) &&
14 (CONFIG_PRIVILEGED_STACK_SIZE % CONFIG_MMU_PAGE_SIZE) == 0);
17 #define ASID_INVALID 0
32 __ASSERT_NO_MSG((((uint32_t)l1_page) & 0xfff) == 0); in compute_regs()
33 __ASSERT_NO_MSG((user_asid == 0) || ((user_asid > 2) && in compute_regs()
36 /* We don't use ring 1, ring 0 ASID must be 1 */ in compute_regs()
38 (user_asid << 16) | 0x000201; in compute_regs()
41 regs->ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000; in compute_regs()
96 "wsr %0, PTEVADDR\n" in xtensa_set_paging()
130 /* The initial rasid after hardware initialization is 0x04030201. in xtensa_init_paging()
[all …]
/Zephyr-latest/include/zephyr/arch/nios2/
Dnios2.h69 __asm__("mov %0, et" : "=r" (et)); in _nios2_read_et()
82 __asm__("mov %0, sp" : "=r" (sp)); in _nios2_read_sp()
104 __asm__ volatile ("flushda (%0)" :: "r" (addr)); in _nios2_dcache_addr_flush()
109 __asm__ volatile ("flushd (%0)" :: "r" (offset)); in z_nios2_dcache_flush()
114 __asm__ volatile ("flushi %0" :: "r" (offset)); in z_nios2_icache_flush()
127 NIOS2_CR_STATUS = 0,
147 * we get errors "Control register number must be in range 0-31 for
201 #define NIOS2_STATUS_PIE_MSK (0x00000001)
202 #define NIOS2_STATUS_PIE_OFST (0)
203 #define NIOS2_STATUS_U_MSK (0x00000002)
[all …]

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