1 /* 2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 #pragma once 6 7 /* SRAM0 (16kB) memory */ 8 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0)) 9 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0)) 10 /* SRAM1 (384kB) memory */ 11 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1)) 12 #define SRAM1_IRAM_START (SRAM1_DRAM_START + IRAM_DRAM_OFFSET) 13 #define SRAM1_SIZE DT_REG_SIZE(DT_NODELABEL(sram1)) 14 /* ICache size is fixed to 16KB on ESP32-C3 */ 15 #define ICACHE_SIZE SRAM0_SIZE 16 17 /** Simplified memory map for the bootloader. 18 * Make sure the bootloader can load into main memory without overwriting itself. 19 * 20 * ESP32-C3 ROM static data usage is as follows: 21 * - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only 22 * - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup 23 * - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) 24 * 25 * The 2nd stage bootloader can take space up to the end of ROM shared 26 * buffers area (0x3fcdc710). 27 */ 28 29 /* The offset between Dbus and Ibus. 30 * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. 31 */ 32 #define IRAM_DRAM_OFFSET 0x700000 33 #define DRAM_BUFFERS_START 0x3fccae00 34 #define DRAM_BUFFERS_END 0x3fccc000 35 #define DRAM_STACK_START 0x3fcdc710 36 #define DRAM_ROM_BSS_DATA_START 0x3fcde710 37 38 /* Set the limit for the application runtime dynamic allocations */ 39 #define DRAM_RESERVED_START DRAM_BUFFERS_END 40 41 /* Base address used for calculating memory layout 42 * counted from Dbus backwards and back to the Ibus 43 */ 44 #define BOOTLOADER_USER_DRAM_END DRAM_BUFFERS_START 45 46 /* For safety margin between bootloader data section and startup stacks */ 47 #define BOOTLOADER_STACK_OVERHEAD 0x0 48 /* These lengths can be adjusted, if necessary: */ 49 #define BOOTLOADER_DRAM_SEG_LEN 0x9800 50 #define BOOTLOADER_IRAM_SEG_LEN 0x9800 51 #define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400 52 53 /* Start of the lower region is determined by region size and the end of the higher region */ 54 #define BOOTLOADER_IRAM_LOADER_SEG_END \ 55 (BOOTLOADER_USER_DRAM_END + BOOTLOADER_STACK_OVERHEAD + IRAM_DRAM_OFFSET) 56 #define BOOTLOADER_IRAM_LOADER_SEG_START \ 57 (BOOTLOADER_IRAM_LOADER_SEG_END - BOOTLOADER_IRAM_LOADER_SEG_LEN) 58 #define BOOTLOADER_IRAM_SEG_START \ 59 (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) 60 #define BOOTLOADER_DRAM_SEG_START \ 61 (BOOTLOADER_IRAM_SEG_START - IRAM_DRAM_OFFSET - BOOTLOADER_DRAM_SEG_LEN) 62 63 /* Flash */ 64 #ifdef CONFIG_FLASH_SIZE 65 #define FLASH_SIZE CONFIG_FLASH_SIZE 66 #else 67 #define FLASH_SIZE 0x400000 68 #endif 69 70 /* Cached memory */ 71 #define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE 72 #define IROM_SEG_ORG 0x42000000 73 #define IROM_SEG_LEN FLASH_SIZE 74 #define DROM_SEG_ORG 0x3c000000 75 #define DROM_SEG_LEN FLASH_SIZE 76
