Lines Matching +full:0 +full:x400000

53 #define ALT_CPU_BIG_ENDIAN 0
54 #define ALT_CPU_BREAK_ADDR 0x00200820
58 #define ALT_CPU_CPU_ID_VALUE 0x00000000
60 #define ALT_CPU_DATA_ADDR_WIDTH 0x17
61 #define ALT_CPU_DCACHE_LINE_SIZE 0
62 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
63 #define ALT_CPU_DCACHE_SIZE 0
64 #define ALT_CPU_EXCEPTION_ADDR 0x00400020
65 #define ALT_CPU_FLASH_ACCELERATOR_LINES 0
66 #define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
76 #define ALT_CPU_ICACHE_LINE_SIZE 0
77 #define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
78 #define ALT_CPU_ICACHE_SIZE 0
79 #define ALT_CPU_INST_ADDR_WIDTH 0x17
82 #define ALT_CPU_RESET_ADDR 0x00000000
90 #define ALT_LOG_PORT_BASE 0x0
93 #define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
97 #define ALT_STDERR_BASE 0x201000
103 #define ALT_STDIN_BASE 0x201000
109 #define ALT_STDOUT_BASE 0x201000
123 #define A_16550_UART_0_BASE 0x440000
126 #define A_16550_UART_0_FIO_HWFC 0
127 #define A_16550_UART_0_FIO_SWFC 0
130 #define A_16550_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
153 #define JTAG_UART_0_BASE 0x201000
154 #define JTAG_UART_0_IRQ 0
155 #define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
171 #define ONCHIP_FLASH_0_CSR_BASE 0x200000
176 #define ONCHIP_FLASH_0_CSR_READ_ONLY_MODE 0
178 #define ONCHIP_FLASH_0_CSR_SECTOR1_END_ADDR 0x7fff
179 #define ONCHIP_FLASH_0_CSR_SECTOR1_START_ADDR 0
181 #define ONCHIP_FLASH_0_CSR_SECTOR2_END_ADDR 0xffff
182 #define ONCHIP_FLASH_0_CSR_SECTOR2_START_ADDR 0x8000
184 #define ONCHIP_FLASH_0_CSR_SECTOR3_END_ADDR 0x6ffff
185 #define ONCHIP_FLASH_0_CSR_SECTOR3_START_ADDR 0x10000
187 #define ONCHIP_FLASH_0_CSR_SECTOR4_END_ADDR 0xb7fff
188 #define ONCHIP_FLASH_0_CSR_SECTOR4_START_ADDR 0x70000
189 #define ONCHIP_FLASH_0_CSR_SECTOR5_ENABLED 0
190 #define ONCHIP_FLASH_0_CSR_SECTOR5_END_ADDR 0xffffffff
191 #define ONCHIP_FLASH_0_CSR_SECTOR5_START_ADDR 0xffffffff
202 #define ONCHIP_FLASH_0_DATA_BASE 0x0
207 #define ONCHIP_FLASH_0_DATA_READ_ONLY_MODE 0
209 #define ONCHIP_FLASH_0_DATA_SECTOR1_END_ADDR 0x7fff
210 #define ONCHIP_FLASH_0_DATA_SECTOR1_START_ADDR 0
212 #define ONCHIP_FLASH_0_DATA_SECTOR2_END_ADDR 0xffff
213 #define ONCHIP_FLASH_0_DATA_SECTOR2_START_ADDR 0x8000
215 #define ONCHIP_FLASH_0_DATA_SECTOR3_END_ADDR 0x6ffff
216 #define ONCHIP_FLASH_0_DATA_SECTOR3_START_ADDR 0x10000
218 #define ONCHIP_FLASH_0_DATA_SECTOR4_END_ADDR 0xb7fff
219 #define ONCHIP_FLASH_0_DATA_SECTOR4_START_ADDR 0x70000
220 #define ONCHIP_FLASH_0_DATA_SECTOR5_ENABLED 0
221 #define ONCHIP_FLASH_0_DATA_SECTOR5_END_ADDR 0xffffffff
222 #define ONCHIP_FLASH_0_DATA_SECTOR5_START_ADDR 0xffffffff
233 #define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
234 #define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
235 #define ONCHIP_MEMORY2_0_BASE 0x400000
237 #define ONCHIP_MEMORY2_0_DUAL_PORT 0
240 #define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 0
245 #define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
248 #define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
262 #define TIMER_0_ALWAYS_RUN 0
263 #define TIMER_0_BASE 0x440200
265 #define TIMER_0_FIXED_PERIOD 0
268 #define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
274 #define TIMER_0_RESET_OUTPUT 0
278 #define TIMER_0_TIMEOUT_PULSE_OUTPUT 0