1 /* 2 * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 #pragma once 6 7 /* SRAM0 (16kB) memory */ 8 #define SRAM0_IRAM_START DT_REG_ADDR(DT_NODELABEL(sram0)) 9 #define SRAM0_SIZE DT_REG_SIZE(DT_NODELABEL(sram0)) 10 11 /* SRAM1 (256kB) memory */ 12 #define SRAM1_IRAM_START (SRAM1_DRAM_START + IRAM_DRAM_OFFSET) 13 #define SRAM1_DRAM_START DT_REG_ADDR(DT_NODELABEL(sram1)) 14 #define SRAM1_SIZE DT_REG_SIZE(DT_NODELABEL(sram1)) 15 16 /* ICache size is fixed to 16KB on ESP32-C2 */ 17 #define ICACHE_SIZE SRAM0_SIZE 18 19 /** Simplified memory map for the bootloader. 20 * Make sure the bootloader can load into main memory without overwriting itself. 21 * 22 * ESP32-C2 ROM static data usage is as follows: 23 * - 0x3fccb264 - 0x3fcdcb70: Shared buffers, used in UART/USB/SPI download mode only 24 * - 0x3fcdcb70 - 0x3fcdeb70: PRO CPU stack, can be reclaimed as heap after RTOS startup 25 * - 0x3fcdeb70 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) 26 * 27 * The 2nd stage bootloader can take space up to the end of ROM shared 28 * buffers area (0x3fcdcb70). 29 */ 30 31 /* The offset between Dbus and Ibus. 32 * Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses. 33 */ 34 #define IRAM_DRAM_OFFSET 0x6e0000 35 36 #define DRAM_BUFFERS_START 0x3fccb264 37 #define DRAM_STACK_START 0x3fcdcb70 38 #define DRAM_ROM_BSS_DATA_START 0x3fcdeb70 39 40 #define DRAM_RESERVED_START DRAM_STACK_START 41 42 /* For safety margin between bootloader data section and startup stacks */ 43 #define BOOTLOADER_STACK_OVERHEAD 0x0 44 /* These lengths can be adjusted, if necessary: */ 45 #define BOOTLOADER_DRAM_SEG_LEN 0xb000 46 #define BOOTLOADER_IRAM_SEG_LEN 0xc800 47 #define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400 48 49 /* Base address used for calculating memory layout 50 * counted from Dbus backwards and back to the Ibus 51 */ 52 #define BOOTLOADER_USER_DRAM_END (DRAM_BUFFERS_START + BOOTLOADER_STACK_OVERHEAD) 53 54 /* Start of the lower region is determined by region size and the end of the higher region */ 55 #define BOOTLOADER_IRAM_LOADER_SEG_START \ 56 (BOOTLOADER_USER_DRAM_END - BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET) 57 #define BOOTLOADER_IRAM_SEG_START \ 58 (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN) 59 #define BOOTLOADER_DRAM_SEG_START \ 60 (BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN - IRAM_DRAM_OFFSET) 61 62 /* Flash */ 63 #ifdef CONFIG_FLASH_SIZE 64 #define FLASH_SIZE CONFIG_FLASH_SIZE 65 #else 66 #define FLASH_SIZE 0x400000 67 #endif 68 69 /* Cached memory */ 70 #define CACHE_ALIGN CONFIG_MMU_PAGE_SIZE 71 #define IROM_SEG_ORG 0x42000000 72 #define IROM_SEG_LEN FLASH_SIZE 73 #define DROM_SEG_ORG 0x3c000000 74 #define DROM_SEG_LEN FLASH_SIZE 75
