1/* SPDX-License-Identifier: Apache-2.0 */
2
3/dts-v1/;
4
5#include <arm/armv7-m.dtsi>
6#include <zephyr/dt-bindings/i2c/i2c.h>
7#include <zephyr/dt-bindings/input/input-event-codes.h>
8
9/ {
10	compatible = "arm,mps2";
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	aliases {
15		led0 = &led_0;
16		led1 = &led_1;
17		sw0 = &user_button_0;
18		sw1 = &user_button_1;
19		watchdog0 = &wdog0;
20	};
21
22	chosen {
23		zephyr,console = &uart0;
24		zephyr,shell-uart = &uart0;
25		zephyr,uart-pipe = &uart1;
26		zephyr,sram = &sram0;
27		zephyr,flash = &flash0;
28	};
29
30	leds {
31		compatible = "gpio-leds";
32		led_0: led_0 {
33			gpios = <&gpio_led0 0>;
34			label = "USERLED0";
35		};
36		led_1: led_1 {
37			gpios = <&gpio_led0 1>;
38			label = "USERLED1";
39		};
40	};
41
42	gpio_keys {
43		compatible = "gpio-keys";
44		user_button_0: button_0 {
45			label = "USERPB0";
46			gpios = <&gpio_button 0>;
47			zephyr,code = <INPUT_KEY_0>;
48		};
49		user_button_1: button_1 {
50			label = "USERPB1";
51			gpios = <&gpio_button 1>;
52			zephyr,code = <INPUT_KEY_1>;
53		};
54	};
55
56	cpus {
57		#address-cells = <1>;
58		#size-cells = <0>;
59
60		cpu@0 {
61			compatible = "arm,cortex-m3";
62			reg = <0>;
63		};
64	};
65
66	sram0: memory@20000000 {
67		compatible = "mmio-sram";
68		reg = <0x20000000 0x400000>;
69	};
70
71	flash0: flash@0 {
72		compatible = "soc-nv-flash";
73		reg = <0 0x400000>;
74	};
75
76	sim_flash_controller: sim_flash_controller {
77		compatible = "zephyr,sim-flash";
78
79		#address-cells = <1>;
80		#size-cells = <1>;
81		erase-value = <0x00>;
82
83		flash_sim0: flash_sim@0 {
84			compatible = "soc-nv-flash";
85			reg = <0x00000000 0x8000>;
86
87			erase-block-size = <1024>;
88			write-block-size = <4>;
89
90			partitions {
91				compatible = "fixed-partitions";
92				#address-cells = <1>;
93				#size-cells = <1>;
94
95				storage_partition: partition@0 {
96					label = "storage_partition";
97					reg = <0x00000000 0x8000>;
98				};
99			};
100		};
101	};
102
103	sysclk: system-clock {
104		compatible = "fixed-clock";
105		clock-frequency = <25000000>;
106		#clock-cells = <0>;
107	};
108
109	soc {
110		timer0: timer@40000000 {
111			compatible = "arm,cmsdk-timer";
112			reg = <0x40000000 0x1000>;
113			interrupts = <8 3>;
114		};
115
116		timer1: timer@40001000 {
117			compatible = "arm,cmsdk-timer";
118			reg = <0x40001000 0x1000>;
119			interrupts = <9 3>;
120		};
121
122		dtimer0: dtimer@40002000 {
123			compatible = "arm,cmsdk-dtimer";
124			reg = <0x40002000 0x1000>;
125			interrupts = <10 3>;
126		};
127
128		uart0: uart@40004000 {
129			compatible = "arm,cmsdk-uart";
130			reg = <0x40004000 0x1000>;
131			interrupts = <1 3 0 3>;
132			interrupt-names = "tx", "rx";
133			clocks = <&sysclk>;
134			current-speed = <115200>;
135		};
136
137		uart1: uart@40005000 {
138			compatible = "arm,cmsdk-uart";
139			reg = <0x40005000 0x1000>;
140			interrupts = <3 3 2 3>;
141			interrupt-names = "tx", "rx";
142			clocks = <&sysclk>;
143			current-speed = <115200>;
144		};
145
146		uart2: uart@40006000 {
147			compatible = "arm,cmsdk-uart";
148			reg = <0x40006000 0x1000>;
149			interrupts = <5 3 4 3>;
150			interrupt-names = "tx", "rx";
151			clocks = <&sysclk>;
152			current-speed = <115200>;
153		};
154
155		uart3: uart@40007000 {
156			compatible = "arm,cmsdk-uart";
157			reg = <0x40007000 0x1000>;
158			interrupts = <19 3 18 3>;
159			interrupt-names = "tx", "rx";
160			clocks = <&sysclk>;
161			current-speed = <115200>;
162		};
163
164		wdog0: wdog@40008000 {
165			compatible = "arm,cmsdk-watchdog";
166			clocks = <&sysclk>;
167			reg = <0x40008000 0x1000>;
168		};
169
170		uart4: uart@40009000 {
171			compatible = "arm,cmsdk-uart";
172			reg = <0x40009000 0x1000>;
173			interrupts = <21 3 20 3>;
174			interrupt-names = "tx", "rx";
175			clocks = <&sysclk>;
176			current-speed = <115200>;
177		};
178
179		gpio0: gpio@40010000 {
180			compatible = "arm,cmsdk-gpio";
181			reg = <0x40010000 0x1000>;
182			interrupts = <6 3>;
183			gpio-controller;
184			#gpio-cells = <2>;
185		};
186
187		gpio1: gpio@40011000 {
188			compatible = "arm,cmsdk-gpio";
189			reg = <0x40011000 0x1000>;
190			interrupts = <7 3>;
191			gpio-controller;
192			#gpio-cells = <2>;
193		};
194
195		gpio2: gpio@40012000 {
196			compatible = "arm,cmsdk-gpio";
197			reg = <0x40012000 0x1000>;
198			interrupts = <16 3>;
199			gpio-controller;
200			#gpio-cells = <2>;
201		};
202
203		gpio3: gpio@40013000 {
204			compatible = "arm,cmsdk-gpio";
205			reg = <0x40013000 0x1000>;
206			interrupts = <17 3>;
207			gpio-controller;
208			#gpio-cells = <2>;
209		};
210
211		eth0: eth@40200000 {
212			/* Linux has "smsc,lan9115" */
213			compatible = "smsc,lan9220";
214			/* Such a big size from memory map in AN385 */
215			/* Actual reg range is ~0x200 */
216			reg = <0x40200000 0x100000>;
217			interrupts = <13 3>;
218		};
219
220		i2c_touch: i2c@40022000 {
221			compatible = "arm,versatile-i2c";
222			clock-frequency = <I2C_BITRATE_STANDARD>;
223			#address-cells = <1>;
224			#size-cells = <0>;
225			reg = <0x40022000 0x1000>;
226		};
227
228		i2c_audio_conf: i2c@40023000 {
229			compatible = "arm,versatile-i2c";
230			clock-frequency = <I2C_BITRATE_STANDARD>;
231			#address-cells = <1>;
232			#size-cells = <0>;
233			reg = <0x40023000 0x1000>;
234		};
235
236		i2c_shield0: i2c@40029000 {
237			compatible = "arm,versatile-i2c";
238			clock-frequency = <I2C_BITRATE_STANDARD>;
239			#address-cells = <1>;
240			#size-cells = <0>;
241			reg = <0x40029000 0x1000>;
242		};
243
244		i2c_shield1: i2c@4002a000 {
245			compatible = "arm,versatile-i2c";
246			clock-frequency = <I2C_BITRATE_STANDARD>;
247			#address-cells = <1>;
248			#size-cells = <0>;
249			reg = <0x4002a000 0x1000>;
250		};
251
252		gpio_led0: mps2_fpgaio@40028000 {
253			compatible = "arm,mps2-fpgaio-gpio";
254
255			reg = <0x40028000 0x4>;
256			gpio-controller;
257			#gpio-cells = <1>;
258			ngpios = <2>;
259		};
260
261		gpio_button: mps2_fpgaio@40028008 {
262			compatible = "arm,mps2-fpgaio-gpio";
263
264			reg = <0x40028008 0x4>;
265			gpio-controller;
266			#gpio-cells = <1>;
267			ngpios = <2>;
268		};
269
270		gpio_misc: mps2_fpgaio@4002804c {
271			compatible = "arm,mps2-fpgaio-gpio";
272
273			reg = <0x4002804c 0x4>;
274			gpio-controller;
275			#gpio-cells = <1>;
276			ngpios = <10>;
277		};
278
279	};
280};
281
282&nvic {
283	arm,num-irq-priority-bits = <3>;
284};
285