Lines Matching +full:0 +full:x400000
13 BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) &&
14 (CONFIG_PRIVILEGED_STACK_SIZE % CONFIG_MMU_PAGE_SIZE) == 0);
17 #define ASID_INVALID 0
32 __ASSERT_NO_MSG((((uint32_t)l1_page) & 0xfff) == 0); in compute_regs()
33 __ASSERT_NO_MSG((user_asid == 0) || ((user_asid > 2) && in compute_regs()
36 /* We don't use ring 1, ring 0 ASID must be 1 */ in compute_regs()
38 (user_asid << 16) | 0x000201; in compute_regs()
41 regs->ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000; in compute_regs()
96 "wsr %0, PTEVADDR\n" in xtensa_set_paging()
130 /* The initial rasid after hardware initialization is 0x04030201. in xtensa_init_paging()
131 * 1 is hardwired to ring 0, other slots must be different in xtensa_init_paging()
132 * from each other and must not be 0. in xtensa_init_paging()
137 initial_rasid = 0xff030201; in xtensa_init_paging()
151 uint32_t idtlb_pte = (regs.ptevaddr & 0xe0000000) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
152 uint32_t idtlb_stk = (((uint32_t)®s) & ~0xfff) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
153 uint32_t iitlb_pc = (((uint32_t)&z_xt_init_pc) & ~0xfff) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
165 "wsr %0, PTEVADDR\n" in xtensa_init_paging()
183 for (uint32_t i = 0; i < 8; i++) { in xtensa_init_paging()
184 uint32_t ixtlb = (i * 0x20000000) | XCHAL_SPANNING_WAY; in xtensa_init_paging()
187 __asm__ volatile("iitlb %0" :: "r"(ixtlb)); in xtensa_init_paging()
190 __asm__ volatile("idtlb %0" :: "r"(ixtlb)); in xtensa_init_paging()