1/*
2 * Copyright 2024 Myeonghyeon Park <myeonghyeon@tsnlab.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm64/armv8-a.dtsi>
8#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-a76";
18			reg = <0>;
19		};
20	};
21
22	interrupt-parent = <&gic>;
23
24	timer {
25		compatible = "arm,armv8-timer";
26		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
27			      IRQ_DEFAULT_PRIORITY>,
28			     <GIC_PPI 14 IRQ_TYPE_LEVEL
29			      IRQ_DEFAULT_PRIORITY>,
30			     <GIC_PPI 11 IRQ_TYPE_LEVEL
31			      IRQ_DEFAULT_PRIORITY>,
32			     <GIC_PPI 10 IRQ_TYPE_LEVEL
33			      IRQ_DEFAULT_PRIORITY>;
34	};
35
36	soc {
37		#address-cells = <2>;
38		#size-cells = <1>;
39
40		sram0: memory@200000 {
41			device_type = "memory";
42			compatible = "mmio-sram";
43			reg = <0x0 0x200000 0x80000>;
44		};
45
46		gic: interrupt-controller@107fff9000 {
47			compatible = "arm,gic-v2", "arm,gic";
48			reg = <0x10 0x7fff9000 0x1000>,
49			      <0x10 0x7fffa000 0x2000>;
50			interrupt-controller;
51			#interrupt-cells = <4>;
52			status = "okay";
53		};
54
55		gpio2@107d517c00 {
56			compatible = "simple-bus";
57			reg = <0x10 0x7d517c00 0x40>;
58
59			#address-cells = <1>;
60			#size-cells = <0>;
61			gio_aon: gpio@0 {
62				compatible = "brcm,brcmstb-gpio";
63				reg = <0>;
64				gpio-controller;
65				#gpio-cells = <2>;
66				ngpios = <17>;
67				status = "disabled";
68			};
69		};
70
71		uart10: serial@107d001000 {
72			compatible = "arm,pl011";
73			reg = <0x10 0x7d001000 0x200>;
74			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL
75				      IRQ_DEFAULT_PRIORITY>;
76			interrupt-names = "irq_121";
77			clocks = <&clk_uart>;
78			status = "disabled";
79		};
80
81	};
82
83	clocks {
84		clk_uart: clk_uart {
85			compatible = "fixed-clock";
86			clock-frequency = <44236800>;
87			#clock-cells = <0>;
88		};
89	};
90
91	axi {
92		#address-cells = <2>;
93		#size-cells = <1>;
94
95		pcie2: pcie@1000120000 {
96			compatible = "brcm,brcmstb-pcie";
97			reg = <0x10 0x120000 0x9310>,
98			      <0x0 0x410000 0x4000>,
99			      <0x0 0x0 0x400000>,
100			      <0x0 0x400000 0x4000>;
101			#address-cells = <3>;
102			#size-cells = <2>;
103			ranges = <0x02000000 0x0 0x0 0x1f 0x0 0x00 0xfffffffc>,
104				 <0x43000000 0x4 0x0 0x1c 0x0 0x03 0x00000000>,
105				 <0x02000000 0x0 0x0 0x1f 0x0 0x00 0x00400000>;
106			status = "okay";
107
108			rp1 {
109				#address-cells = <2>;
110				#size-cells = <1>;
111
112				gpio0: gpio@1f000d0000 {
113					compatible = "simple-bus";
114					reg = <0x1f 0xd0000 0x30000>;
115					#address-cells = <1>;
116					#size-cells = <0>;
117
118					gpio0_0: gpio@0 {
119						compatible = "raspberrypi,rp1-gpio";
120						reg = <0x0 0x10000 0x20000>;
121						#gpio-cells = <2>;
122						gpio-controller;
123						ngpios = <28>;
124						status = "disabled";
125					};
126
127					gpio0_1: gpio@4000 {
128						compatible = "raspberrypi,rp1-gpio";
129						reg = <0x4000 0x14000 0x24000>;
130						#gpio-cells = <2>;
131						gpio-controller;
132						ngpios = <6>;
133						status = "disabled";
134					};
135
136					gpio0_2: gpio@8000 {
137						compatible = "raspberrypi,rp1-gpio";
138						reg = <0x8000 0x18000 0x28000>;
139						#gpio-cells = <2>;
140						gpio-controller;
141						ngpios = <20>;
142						status = "disabled";
143					};
144				};
145			};
146		};
147	};
148};
149