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/Zephyr-latest/dts/arm/xilinx/
Dzynqmp_rpu.dtsi12 #size-cells = <0>;
14 cpu@0 {
17 reg = <0>;
29 reg = <0xff310000 0x10000>;
36 remote-ipi-id = <0>;
37 reg = <0xff990200 0x20>,
38 <0xff990220 0x20>,
39 <0xff990040 0x20>,
40 <0xff990060 0x20>;
49 reg = <0xff990260 0x20>,
[all …]
/Zephyr-latest/dts/arm/atmel/
Dsamd20.dtsi11 tc-0 = &tc0;
19 reg = <0x42002000 0x20>;
20 interrupts = <13 0>;
21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
28 reg = <0x42002800 0x20>;
29 interrupts = <15 0>;
30 clocks = <&gclk 0x14>, <&pm 0x20 10>;
37 reg = <0x42003800 0x20>;
38 interrupts = <19 0>;
39 clocks = <&gclk 0x16>, <&pm 0x20 14>;
[all …]
Dsamd21.dtsi13 tcc-0 = &tcc0;
21 reg = <0x41005000 0x1000>;
22 interrupts = <7 0>;
30 reg = <0x41004800 0x50>;
31 interrupts = <6 0>;
39 reg = <0x42003800 0x20>;
40 interrupts = <21 0>;
41 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
48 reg = <0x42002000 0x80>;
49 interrupts = <15 0>;
[all …]
/Zephyr-latest/tests/net/ppp/driver/src/
Dmain.c49 0x7e, 0xff, 0x7d, 0x23, 0xc0, 0x21, 0x7d, 0x21,
50 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
51 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
52 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
53 0xcf, 0x41, 0x7d, 0x27, 0x7d, 0x22, 0x7d, 0x28,
54 0x7d, 0x22, 0xc4, 0xc9, 0x7e,
59 0xc0, 0x21, 0x01, 0x01, 0x00, 0x14, 0x02, 0x06,
60 0x00, 0x00, 0x00, 0x00, 0x05, 0x06, 0x5d, 0x58,
61 0xcf, 0x41, 0x07, 0x02, 0x08, 0x02,
65 0x7e, 0xff, 0x7d, 0x23, 0xc0, 0x21, 0x7d, 0x21,
[all …]
/Zephyr-latest/tests/crypto/tinycrypt/src/
Dhmac.c71 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, in ZTEST()
72 0x0b, 0x0b, in ZTEST()
73 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b in ZTEST()
76 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 in ZTEST()
79 0xb0, 0x34, 0x4c, 0x61, 0xd8, 0xdb, 0x38, 0x53, 0x5c, 0xa8, in ZTEST()
80 0xaf, 0xce, in ZTEST()
81 0xaf, 0x0b, 0xf1, 0x2b, 0x88, 0x1d, 0xc2, 0x00, 0xc9, 0x83, in ZTEST()
82 0x3d, 0xa7, in ZTEST()
83 0x26, 0xe9, 0x37, 0x6c, 0x2e, 0x32, 0xcf, 0xf7 in ZTEST()
87 (void)memset(&h, 0x00, sizeof(h)); in ZTEST()
[all …]
/Zephyr-latest/tests/subsys/mgmt/mcumgr/os_mgmt_echo/src/
Dmain.c17 0x02, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x01, 0x00,
18 0xbf, 0x61, 0x64, 0x78, 0x28, 0x73, 0x68, 0x6f,
19 0x72, 0x74, 0x20, 0x4d, 0x43, 0x55, 0x4d, 0x47,
20 0x52, 0x20, 0x74, 0x65, 0x73, 0x74, 0x20, 0x61,
21 0x70, 0x70, 0x6c, 0x69, 0x63, 0x61, 0x74, 0x69,
22 0x6f, 0x6e, 0x20, 0x6d, 0x65, 0x73, 0x73, 0x61,
23 0x67, 0x65, 0x2e, 0x2e, 0x2e, 0xff,
28 0x03, 0x00, 0x00, 0x2e, 0x00, 0x00, 0x01, 0x00,
29 0xbf, 0x61, 0x72, 0x78, 0x28, 0x73, 0x68, 0x6f,
30 0x72, 0x74, 0x20, 0x4d, 0x43, 0x55, 0x4d, 0x47,
[all …]
/Zephyr-latest/dts/arm/renesas/ra/
Dra4-cm4-common.dtsi13 reg = <0x400400c0 0x20>;
22 reg = <0x400400e0 0x20>;
31 reg = <0x40040100 0x20>;
40 reg = <0x40040120 0x20>;
49 reg = <0x40070040 0x20>;
50 interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_RXI>,
51 <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_TXI>,
52 <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_TEI>,
53 <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_ERI>,
54 <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_AM>;
Dra-cm4-common.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #clock-cells = <0>;
58 #clock-cells = <0>;
63 #clock-cells = <0>;
68 mul = <8 0>;
[all …]
/Zephyr-latest/drivers/sensor/tdk/icm42605/
Dicm42605_reg.h10 /* BANK 0 */
11 #define REG_DEVICE_CONFIG 0x11
12 #define REG_DRIVE_CONFIG 0x13
13 #define REG_INT_CONFIG 0x14
14 #define REG_FIFO_CONFIG 0x16
15 #define REG_TEMP_DATA1 0x1D
16 #define REG_TEMP_DATA0 0x1E
17 #define REG_ACCEL_DATA_X1 0x1F
18 #define REG_ACCEL_DATA_X0 0x20
19 #define REG_ACCEL_DATA_Y1 0x21
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc1200_rf.h32 0x6F, /* SYNC3 */
33 0x4E,
34 0x90,
35 0x4E,
36 0xE5,
37 0x23,
38 0x47,
39 0x0B,
40 0x56,
41 0x19, /* 0x14 */
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra2/
Dra2xx.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
29 reg = <0x4001e000 0x1000>;
35 reg = <0x40040000 0x20>;
36 port = <0>;
45 reg = <0x40040020 0x20>;
55 reg = <0x40040040 0x20>;
65 reg = <0x40040060 0x20>;
75 reg = <0x40040080 0x20>;
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/
DW25Q512JVFIQ_FCB.c20 .deviceModeArg = 0x02,
21 .configCmdEnable = 0,
22 .deviceType = 0x1,
25 .sflashA1Size = 0x4000000U,
26 .sflashA2Size = 0,
27 .sflashB1Size = 0,
28 .sflashB2Size = 0,
31 [0] = FC_FLEXSPI_LUT_SEQ(
32 FC_CMD_SDR, FC_FLEXSPI_1PAD, 0xEC,
34 0x20),
[all …]
/Zephyr-latest/drivers/display/
Ddisplay_st7789v.h11 #define ST7789V_CMD_NOP 0x00
12 #define ST7789V_CMD_SW_RESET 0x01
14 #define ST7789V_CMD_SLEEP_IN 0x10
15 #define ST7789V_CMD_SLEEP_OUT 0x11
16 #define ST7789V_CMD_INV_OFF 0x20
17 #define ST7789V_CMD_INV_ON 0x21
18 #define ST7789V_CMD_GAMSET 0x26
19 #define ST7789V_CMD_DISP_OFF 0x28
20 #define ST7789V_CMD_DISP_ON 0x29
22 #define ST7789V_CMD_CASET 0x2a
[all …]
/Zephyr-latest/boards/nxp/rd_rw612_bga/
DMX25U51245GZ4I00_FCB.c19 .deviceModeArg = 0xC740,
20 .configCmdEnable = 0,
21 .deviceType = 0x1,
24 .sflashA1Size = 0x4000000U,
25 .sflashA2Size = 0,
26 .sflashB1Size = 0,
27 .sflashB2Size = 0,
30 [0] = FC_FLEXSPI_LUT_SEQ(
32 0xEC, FC_RADDR_SDR,
33 FC_FLEXSPI_4PAD, 0x20),
[all …]
/Zephyr-latest/arch/sparc/core/
Dstack_offsets.h16 #define STACK_FRAME_L0_OFFSET 0x00
17 #define STACK_FRAME_L1_OFFSET 0x04
18 #define STACK_FRAME_L2_OFFSET 0x08
19 #define STACK_FRAME_L3_OFFSET 0x0c
20 #define STACK_FRAME_L4_OFFSET 0x10
21 #define STACK_FRAME_L5_OFFSET 0x14
22 #define STACK_FRAME_L6_OFFSET 0x18
23 #define STACK_FRAME_L7_OFFSET 0x1c
24 #define STACK_FRAME_I0_OFFSET 0x20
25 #define STACK_FRAME_I1_OFFSET 0x24
[all …]
/Zephyr-latest/dts/arm/ambiq/
Dambiq_apollo3_blue.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0x50000>;
79 flash: flash-controller@0 {
81 reg = <0x00000000 0x100000>;
87 flash0: flash@0 {
[all …]
Dambiq_apollo3p_blue.dtsi15 #clock-cells = <0>;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
25 reg = <0>;
32 reg = <0xe0000000 0x1000>;
66 reg = <0x10000000 0x10000>;
73 reg = <0x10010000 0xB0000>;
78 reg = <0x52000000 0x2000000>;
84 reg = <0x54000000 0x2000000>;
90 reg = <0x56000000 0x2000000>;
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra4/
Dra4-cm4-common.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
27 reg = <0xe000ed90 0x40>;
36 reg = <0x4001e000 0x1000>;
41 reg = <0x407e0000 0x10000>;
48 reg = <0x40040000 0x20>;
49 port = <0>;
58 reg = <0x40040020 0x20>;
68 reg = <0x40040040 0x20>;
[all …]
/Zephyr-latest/dts/arm/microchip/
Dmec1501hsz.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0>;
42 reg = <0x000E0000 0x38000>;
47 reg = <0x00118000 0x8000>;
51 i2c-smb-0 = &i2c_smb_0;
61 reg = <0x4000fc00 0x200>;
65 reg = <0x40080100 0x100 0x4000a400 0x100>;
80 reg = <0x4000e000 0x400>;
85 reg = <0x12c 0x14>;
[all …]
Dmec172xnlj.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0>;
48 reg = <0x000C0000 0x58000>;
53 reg = <0x00118000 0x10000>;
61 reg = <0x40002c00 0x400>;
71 reg = <0x40005890 0x20>;
79 reg = <0x400058a0 0x20>;
80 pcrs = <4 0>;
87 reg = <0x400058b0 0x20>;
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_vim.h16 #define VIM_BASE_ADDR DT_REG_ADDR(DT_INST(0, ti_vim))
26 #define VIM_PID (VIM_BASE_ADDR + 0x0000)
27 #define VIM_INFO (VIM_BASE_ADDR + 0x0004)
28 #define VIM_PRIIRQ (VIM_BASE_ADDR + 0x0008)
29 #define VIM_PRIFIQ (VIM_BASE_ADDR + 0x000C)
30 #define VIM_IRQGSTS (VIM_BASE_ADDR + 0x0010)
31 #define VIM_FIQGSTS (VIM_BASE_ADDR + 0x0014)
32 #define VIM_IRQVEC (VIM_BASE_ADDR + 0x0018)
33 #define VIM_FIQVEC (VIM_BASE_ADDR + 0x001C)
34 #define VIM_ACTIRQ (VIM_BASE_ADDR + 0x0020)
[all …]
/Zephyr-latest/dts/arm/renesas/ra/ra6/
Dra6-cm4-common.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
28 reg = <0xe000ed90 0x40>;
37 reg = <0x4001e000 0x1000>;
43 reg = <0x40040000 0x20>;
44 port = <0>;
53 reg = <0x40040020 0x20>;
63 reg = <0x40040040 0x20>;
73 reg = <0x40040060 0x20>;
[all …]
/Zephyr-latest/dts/bindings/i2c/
Dzephyr,i2c-emul-controller.yaml24 example, if we wanted to forward any requests from i2c0@0x20 to i2c1, we
28 forward = <&i2c1 0x20>;
/Zephyr-latest/soc/espressif/common/
DKconfig.defconfig26 default $(dt_node_int_prop_int,/cpus/cpu@0,xtal-freq)
53 default 0x20
81 default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
101 default 0x20
/Zephyr-latest/tests/subsys/modem/modem_ppp/src/
Dmain.c42 static uint8_t ppp_frame_wrapped[] = {0x7E, 0xFF, 0x7D, 0x23, 0xC0, 0x21, 0x7D, 0x21, 0x7D,
43 0x21, 0x7D, 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
45 static uint8_t ppp_frame_unwrapped[] = {0xC0, 0x21, 0x01, 0x01, 0x00, 0x04};
48 0x7E, 0xFF, 0x7D, 0x23, 0x7D, 0x20, 0x21, 0x45, 0x7D, 0x20, 0x7D, 0x20, 0x29, 0x87, 0x6E,
49 0x40, 0x7D, 0x20, 0xE8, 0x7D, 0x31, 0xC1, 0xE9, 0x7D, 0x23, 0xFB, 0x7D, 0x25, 0x20, 0x7D,
50 0x2A, 0x2B, 0x36, 0x26, 0x25, 0x7D, 0x32, 0x8C, 0x3E, 0x7D, 0x20, 0x7D, 0x35, 0xBD, 0xF3,
51 0x2D, 0x7D, 0x20, 0x7D, 0x2B, 0x7D, 0x20, 0x7D, 0x27, 0x7D, 0x20, 0x7D, 0x24, 0x7D, 0x20,
52 0x7D, 0x24, 0x7D, 0x2A, 0x7D, 0x20, 0x7D, 0x2A, 0x7D, 0x20, 0xD4, 0x31, 0x7E};
55 0x45, 0x00, 0x00, 0x29, 0x87, 0x6E, 0x40, 0x00, 0xE8, 0x11, 0xC1, 0xE9, 0x03, 0xFB,
56 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
[all …]

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