Lines Matching +full:0 +full:x20
17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
29 reg = <0x4001e000 0x1000>;
35 reg = <0x40040000 0x20>;
36 port = <0>;
45 reg = <0x40040020 0x20>;
55 reg = <0x40040040 0x20>;
65 reg = <0x40040060 0x20>;
75 reg = <0x40040080 0x20>;
85 reg = <0x400400a0 0x20>;
95 reg = <0x400400c0 0x20>;
105 reg = <0x400400e0 0x20>;
115 reg = <0x40040100 0x20>;
125 reg = <0x40040120 0x20>;
135 reg = <0x40040800 0x3c0>;
143 reg = <0x40070000 0x20>;
148 channel = <0>;
157 reg = <0x40070020 0x20>;
171 reg = <0x40070040 0x20>;
185 reg = <0x40070060 0x20>;
199 reg = <0x40070120 0x20>;
212 #size-cells = <0>;
213 channel = <0>;
214 reg = <0x40072000 0x100>;
221 #size-cells = <0>;
225 reg = <0x40072100 0x100>;
231 channel = <0>;
232 reg = <0x40053000 0x100>;
239 reg = <0x40053100 0x100>;
244 reg = <0x407e0000 0x10000>;
251 channel = <0>;
252 reg = <0x40084000 0x100>;
254 renesas,prescaler = <0>;
267 reg = <0x40084100 0x100>;
269 renesas,prescaler = <0>;
281 reg = <0x01010018 0x20>;
288 reg = <0x40006000 0x1>;
289 channel = <0>;
291 #port-irq-cells = <0>;
297 reg = <0x40006001 0x1>;
300 #port-irq-cells = <0>;
306 reg = <0x40006002 0x1>;
309 #port-irq-cells = <0>;
315 reg = <0x40006003 0x1>;
318 #port-irq-cells = <0>;
324 reg = <0x40006004 0x1>;
327 #port-irq-cells = <0>;
333 reg = <0x40006005 0x1>;
336 #port-irq-cells = <0>;
342 reg = <0x40006006 0x1>;
345 #port-irq-cells = <0>;
351 reg = <0x40006007 0x1>;
354 #port-irq-cells = <0>;
363 reg = <0x40078000 0x100>;