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/Linux-v6.1/drivers/net/ethernet/mediatek/
Dmtk_ppe_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
9 #define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
10 #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
11 #define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
12 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
13 #define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
14 #define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
15 #define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
16 #define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
[all …]
/Linux-v6.1/drivers/media/platform/samsung/exynos4-is/
Dfimc-reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
[all …]
/Linux-v6.1/include/soc/mscc/
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
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/Linux-v6.1/include/linux/soc/mediatek/
Dinfracfg.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6)
34 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10)
35 #define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11)
37 #define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23)
39 #define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22)
40 #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
42 #define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7)
43 #define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11))
44 #define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14))
[all …]
/Linux-v6.1/drivers/net/wireless/mediatek/mt76/
Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
40 #define MT_TXD1_LONG_FORMAT BIT(31)
41 #define MT_TXD1_TGID BIT(30)
43 #define MT_TXD1_AMSDU BIT(23)
48 #define MT_TXD1_ETH_802_3 BIT(15)
49 #define MT_TXD1_VTA BIT(10)
52 #define MT_TXD2_FIX_RATE BIT(31)
53 #define MT_TXD2_FIXED_RATE BIT(30)
57 #define MT_TXD2_HTC_VLD BIT(13)
58 #define MT_TXD2_DURATION BIT(12)
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/Linux-v6.1/drivers/comedi/drivers/
Dni_tio_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
17 #define GI_ARM BIT(0)
18 #define GI_SAVE_TRACE BIT(1)
19 #define GI_LOAD BIT(2)
20 #define GI_DISARM BIT(4)
23 #define GI_WRITE_SWITCH BIT(7)
24 #define GI_SYNC_GATE BIT(8)
25 #define GI_LITTLE_BIG_ENDIAN BIT(9)
26 #define GI_BANK_SWITCH_START BIT(10)
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Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/Linux-v6.1/drivers/net/ipa/reg/
Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[all …]
Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[all …]
Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[all …]
Dipa_reg-v4.9.c1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[all …]
Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
11 [COMP_CFG_ENABLE] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 /* Bits 5-31 reserved */
22 [CLKON_RX] = BIT(0),
23 [CLKON_PROC] = BIT(1),
24 [TX_WRAPPER] = BIT(2),
[all …]
/Linux-v6.1/drivers/staging/media/atomisp/pci/isp/kernels/ctc/ctc_1.0/
Dia_css_ctc_types.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 * CSS-API header file for Chroma Tone Control parameters.
27 * IA_CSS_CTC_COEF_SHIFT(=13) includes not only the fractional bits
29 * from 13bit precision to 8bit precision.
32 * Input(Chorma) : s0.12 (13bit precision)
33 * Output(Chorma): s0.7 (8bit precision)
36 #define IA_CSS_CTC_COEF_SHIFT 13
41 #define IA_CSS_VAMEM_1_CTC_TABLE_SIZE BIT(IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2)
56 * (ISP1: CTC1 (CTC by look-up table) is used.)
61 u[ce_gain_exp].[13-ce_gain_exp], [0,8191],
[all …]
/Linux-v6.1/drivers/gpu/drm/mediatek/
Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
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/Linux-v6.1/drivers/net/pcs/
Dpcs-xpcs.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #define DW_VENDOR BIT(15)
16 #define DW_USXGMII_RST BIT(10)
17 #define DW_USXGMII_EN BIT(9)
22 #define DW_USXGMII_FULL BIT(8)
23 #define DW_USXGMII_SS_MASK (BIT(13) | BIT(6) | BIT(5))
24 #define DW_USXGMII_10000 (BIT(13) | BIT(6))
25 #define DW_USXGMII_5000 (BIT(13) | BIT(5))
26 #define DW_USXGMII_2500 (BIT(5))
27 #define DW_USXGMII_1000 (BIT(6))
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/Linux-v6.1/drivers/gpu/drm/vc4/
Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
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/Linux-v6.1/drivers/mmc/host/
Dmeson-mx-sdhc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
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/Linux-v6.1/drivers/power/supply/
Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
492 [F_CUR_ILIM_VAL] = REG_FIELD(CUR_ILIM_VAL, 0, 13),
493 [F_SEL_ILIM_VAL] = REG_FIELD(SEL_ILIM_VAL, 0, 13),
494 [F_IBUS_LIM_SET] = REG_FIELD(IBUS_LIM_SET, 5, 13),
495 [F_ICC_LIM_SET] = REG_FIELD(ICC_LIM_SET, 5, 13),
496 [F_IOTG_LIM_SET] = REG_FIELD(IOTG_LIM_SET, 5, 13),
499 [F_VRBOOST_EN] = REG_FIELD(VIN_CTRL_SET, 12, 13),
509 [F_ILIM_AUTO_DISEN] = REG_FIELD(CHGOP_SET1, 13, 13),
518 [F_DCDC_1MS_SEL] = REG_FIELD(CHGOP_SET2, 12, 13),
539 [F_ICHG_SET] = REG_FIELD(ICHG_SET, 6, 13),
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/Linux-v6.1/drivers/net/ethernet/microchip/sparx5/
Dsparx5_main_regs.h1 /* SPDX-License-Identifier: GPL-2.0+
7 /* This file is autogenerated by cml-utils 2022-02-26 14:15:01 +0100.
60 #define ANA_AC_RAM_INIT_RAM_INIT BIT(1)
66 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK BIT(0)
90 #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0)
105 #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0)
120 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA BIT(1)
126 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA BIT(0)
144 #define ANA_AC_STAT_RESET_RESET BIT(0)
165 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE BIT(0)
[all …]
/Linux-v6.1/drivers/net/wireless/ath/ath11k/
Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
88 #define RX_ATTENTION_INFO1_FIRST_MPDU BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS BIT(6)
95 #define RX_ATTENTION_INFO1_NULL_DATA BIT(7)
[all …]
/Linux-v6.1/drivers/clk/stm32/
Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
224 #define RCC_SECCFGR_MLAHBSEC 13
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
[all …]
/Linux-v6.1/sound/soc/mediatek/mt8186/
Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
[all …]
/Linux-v6.1/arch/mips/include/asm/mach-ath79/
Dar71xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)
173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)
174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)
176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)
179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)
[all …]
/Linux-v6.1/drivers/media/platform/st/stm32/dma2d/
Ddma2d-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
8 * based on s5p-g2d
21 #define CR_M2M_PFC BIT(16)
22 #define CR_M2M_BLEND BIT(17)
23 #define CR_R2M (BIT(17) | BIT(16))
24 #define CR_CEIE BIT(13)
25 #define CR_CTCIE BIT(12)
26 #define CR_CAEIE BIT(11)
27 #define CR_TWIE BIT(10)
[all …]
/Linux-v6.1/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
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