Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
20 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
21 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
22 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
23 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
24 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
25 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
26 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
27 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
28 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
29 /* Bit 18 reserved */
30 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
31 [GENQMB_AOOOWR] = BIT(20),
32 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
34 /* Bits 24-29 reserved */
35 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
36 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
42 [CLKON_RX] = BIT(0),
43 [CLKON_PROC] = BIT(1),
44 [TX_WRAPPER] = BIT(2),
45 [CLKON_MISC] = BIT(3),
46 [RAM_ARB] = BIT(4),
47 [FTCH_HPS] = BIT(5),
48 [FTCH_DPS] = BIT(6),
49 [CLKON_HPS] = BIT(7),
50 [CLKON_DPS] = BIT(8),
51 [RX_HPS_CMDQS] = BIT(9),
52 [HPS_DPS_CMDQS] = BIT(10),
53 [DPS_TX_CMDQS] = BIT(11),
54 [RSRC_MNGR] = BIT(12),
55 [CTX_HANDLER] = BIT(13),
56 [ACK_MNGR] = BIT(14),
57 [D_DCPH] = BIT(15),
58 [H_DCPH] = BIT(16),
59 /* Bit 17 reserved */
60 [NTF_TX_CMDQS] = BIT(18),
61 [CLKON_TX_0] = BIT(19),
62 [CLKON_TX_1] = BIT(20),
63 [CLKON_FNR] = BIT(21),
64 [QSB2AXI_CMDQ_L] = BIT(22),
65 [AGGR_WRAPPER] = BIT(23),
66 [RAM_SLAVEWAY] = BIT(24),
67 [CLKON_QMB] = BIT(25),
68 [WEIGHT_ARB] = BIT(26),
69 [GSI_IF] = BIT(27),
70 [CLKON_GLOBAL] = BIT(28),
71 [GLOBAL_2X_CLK] = BIT(29),
72 [DPL_FIFO] = BIT(30),
73 [DRBIP] = BIT(31),
79 [ROUTE_DIS] = BIT(0),
81 [ROUTE_DEF_HDR_TABLE] = BIT(6),
84 /* Bits 22-23 reserved */
85 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
86 /* Bits 25-31 reserved */
101 /* Bits 8-31 reserved */
109 /* Bits 8-15 reserved */
117 [IPV6_ROUTER_HASH] = BIT(0),
118 /* Bits 1-3 reserved */
119 [IPV6_FILTER_HASH] = BIT(4),
120 /* Bits 5-7 reserved */
121 [IPV4_ROUTER_HASH] = BIT(8),
122 /* Bits 9-11 reserved */
123 [IPV4_FILTER_HASH] = BIT(12),
124 /* Bits 13-31 reserved */
130 [IPV6_ROUTER_HASH] = BIT(0),
131 /* Bits 1-3 reserved */
132 [IPV6_FILTER_HASH] = BIT(4),
133 /* Bits 5-7 reserved */
134 [IPV4_ROUTER_HASH] = BIT(8),
135 /* Bits 9-11 reserved */
136 [IPV4_FILTER_HASH] = BIT(12),
137 /* Bits 13-31 reserved */
142 /* Valid bits defined by ipa->available */
147 /* Bits 18-31 reserved */
153 /* Valid bits defined by ipa->available */
157 /* Bits 0-1 reserved */
160 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
161 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
162 [PA_MASK_EN] = BIT(12),
163 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
164 [DUAL_TX_ENABLE] = BIT(17),
165 [SSPND_PA_NO_START_STATE] = BIT(18),
166 /* Bits 19-31 reserved */
173 /* Bits 5-7 reserved */
175 /* Bits 13-15 reserved */
177 /* Bits 21-23 reserved */
179 /* Bits 28-31 reserved */
186 [CONST_NON_IDLE_ENABLE] = BIT(16),
187 /* Bits 17-31 reserved */
194 /* Bits 5-6 reserved */
195 [DPL_TIMESTAMP_SEL] = BIT(7),
197 /* Bits 13-15 reserved */
199 /* Bits 21-31 reserved */
206 /* Bits 9-30 reserved */
207 [DIV_ENABLE] = BIT(31),
216 /* Bits 9-31 reserved */
223 /* Bits 6-7 reserved */
224 [X_MAX_LIM] = GENMASK(13, 8),
225 /* Bits 14-15 reserved */
227 /* Bits 22-23 reserved */
229 /* Bits 30-31 reserved */
237 /* Bits 6-7 reserved */
238 [X_MAX_LIM] = GENMASK(13, 8),
239 /* Bits 14-15 reserved */
241 /* Bits 22-23 reserved */
243 /* Bits 30-31 reserved */
251 /* Bits 6-7 reserved */
252 [X_MAX_LIM] = GENMASK(13, 8),
253 /* Bits 14-15 reserved */
255 /* Bits 22-23 reserved */
257 /* Bits 30-31 reserved */
265 /* Bits 6-7 reserved */
266 [X_MAX_LIM] = GENMASK(13, 8),
267 /* Bits 14-15 reserved */
269 /* Bits 22-23 reserved */
271 /* Bits 30-31 reserved */
278 [FRAG_OFFLOAD_EN] = BIT(0),
281 /* Bit 7 reserved */
282 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
283 /* Bits 9-31 reserved */
290 /* Bits 2-31 reserved */
297 [HDR_OFST_METADATA_VALID] = BIT(6),
299 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
300 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
302 /* Bit 26 reserved */
303 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
311 [HDR_ENDIANNESS] = BIT(0),
312 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
313 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
314 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
316 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
317 /* Bits 14-15 reserved */
321 /* Bits 22-31 reserved */
331 [DCPH_ENABLE] = BIT(3),
333 /* Bits 9-11 reserved */
335 [PIPE_REPLICATION_EN] = BIT(28),
336 [PAD_EN] = BIT(29),
337 [DRBIP_ACL_ENABLE] = BIT(30),
338 /* Bit 31 reserved */
347 /* Bit 11 reserved */
350 [SW_EOF_ACTIVE] = BIT(23),
351 [FORCE_CLOSE] = BIT(24),
352 /* Bit 25 reserved */
353 [HARD_BYTE_LIMIT_EN] = BIT(26),
354 [AGGR_GRAN_SEL] = BIT(27),
355 /* Bits 28-31 reserved */
361 [HOL_BLOCK_EN] = BIT(0),
362 /* Bits 1-31 reserved */
370 /* Bits 5-7 reserved */
371 [TIMER_GRAN_SEL] = BIT(8),
372 /* Bits 9-31 reserved */
380 [SYSPIPE_ERR_DETECTION] = BIT(6),
381 [PACKET_OFFSET_VALID] = BIT(7),
382 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
383 [IGNORE_MIN_PKT_ERR] = BIT(14),
384 /* Bit 15 reserved */
392 /* Bits 2-31 reserved */
400 /* Bits 8-31 reserved */
406 [STATUS_EN] = BIT(0),
408 /* Bits 6-8 reserved */
409 [STATUS_PKT_SUPPRESS] = BIT(9),
410 /* Bits 10-31 reserved */
416 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
417 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
418 [FILTER_HASH_MSK_DST_IP] = BIT(2),
419 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
420 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
421 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
422 [FILTER_HASH_MSK_METADATA] = BIT(6),
424 /* Bits 7-15 reserved */
425 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
426 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
427 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
428 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
429 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
430 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
431 [ROUTER_HASH_MSK_METADATA] = BIT(22),
433 /* Bits 23-31 reserved */
449 [UC_INTR] = BIT(0),
450 /* Bits 1-31 reserved */
455 /* Valid bits defined by ipa->available */
458 /* Valid bits defined by ipa->available */
461 /* Valid bits defined by ipa->available */