Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
20 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
21 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
22 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
23 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
24 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
25 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
26 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
27 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
28 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(17),
29 [QMB_RAM_RD_CACHE_DISABLE] = BIT(19),
30 [GENQMB_AOOOWR] = BIT(20),
31 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
33 /* Bits 25-29 reserved */
34 [GEN_QMB_1_DYNAMIC_ASIZE] = BIT(30),
35 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
41 [CLKON_RX] = BIT(0),
42 [CLKON_PROC] = BIT(1),
43 [TX_WRAPPER] = BIT(2),
44 [CLKON_MISC] = BIT(3),
45 [RAM_ARB] = BIT(4),
46 [FTCH_HPS] = BIT(5),
47 [FTCH_DPS] = BIT(6),
48 [CLKON_HPS] = BIT(7),
49 [CLKON_DPS] = BIT(8),
50 [RX_HPS_CMDQS] = BIT(9),
51 [HPS_DPS_CMDQS] = BIT(10),
52 [DPS_TX_CMDQS] = BIT(11),
53 [RSRC_MNGR] = BIT(12),
54 [CTX_HANDLER] = BIT(13),
55 [ACK_MNGR] = BIT(14),
56 [D_DCPH] = BIT(15),
57 [H_DCPH] = BIT(16),
58 [CLKON_DCMP] = BIT(17),
59 [NTF_TX_CMDQS] = BIT(18),
60 [CLKON_TX_0] = BIT(19),
61 [CLKON_TX_1] = BIT(20),
62 [CLKON_FNR] = BIT(21),
63 [QSB2AXI_CMDQ_L] = BIT(22),
64 [AGGR_WRAPPER] = BIT(23),
65 [RAM_SLAVEWAY] = BIT(24),
66 [CLKON_QMB] = BIT(25),
67 [WEIGHT_ARB] = BIT(26),
68 [GSI_IF] = BIT(27),
69 [CLKON_GLOBAL] = BIT(28),
70 [GLOBAL_2X_CLK] = BIT(29),
71 [DPL_FIFO] = BIT(30),
72 [DRBIP] = BIT(31),
78 [ROUTE_DIS] = BIT(0),
80 [ROUTE_DEF_HDR_TABLE] = BIT(6),
83 /* Bits 22-23 reserved */
84 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
85 /* Bits 25-31 reserved */
100 /* Bits 8-31 reserved */
108 /* Bits 8-15 reserved */
116 [IPV6_ROUTER_HASH] = BIT(0),
117 /* Bits 1-3 reserved */
118 [IPV6_FILTER_HASH] = BIT(4),
119 /* Bits 5-7 reserved */
120 [IPV4_ROUTER_HASH] = BIT(8),
121 /* Bits 9-11 reserved */
122 [IPV4_FILTER_HASH] = BIT(12),
123 /* Bits 13-31 reserved */
129 [IPV6_ROUTER_HASH] = BIT(0),
130 /* Bits 1-3 reserved */
131 [IPV6_FILTER_HASH] = BIT(4),
132 /* Bits 5-7 reserved */
133 [IPV4_ROUTER_HASH] = BIT(8),
134 /* Bits 9-11 reserved */
135 [IPV4_FILTER_HASH] = BIT(12),
136 /* Bits 13-31 reserved */
141 /* Valid bits defined by ipa->available */
146 /* Bits 18-31 reserved */
152 /* Valid bits defined by ipa->available */
156 /* Bits 0-1 reserved */
159 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
160 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
161 [PA_MASK_EN] = BIT(12),
162 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
163 [DUAL_TX_ENABLE] = BIT(17),
164 [SSPND_PA_NO_START_STATE] = BIT(18),
165 /* Bits 19-31 reserved */
172 /* Bits 4-7 reserved */
174 /* Bits 13-15 reserved */
176 /* Bits 21-23 reserved */
178 /* Bits 28-31 reserved */
185 [CONST_NON_IDLE_ENABLE] = BIT(16),
186 /* Bits 17-31 reserved */
193 /* Bits 5-6 reserved */
194 [DPL_TIMESTAMP_SEL] = BIT(7),
196 /* Bits 13-15 reserved */
198 /* Bits 21-31 reserved */
205 /* Bits 9-30 reserved */
206 [DIV_ENABLE] = BIT(31),
221 /* Bits 6-7 reserved */
222 [X_MAX_LIM] = GENMASK(13, 8),
223 /* Bits 14-15 reserved */
225 /* Bits 22-23 reserved */
227 /* Bits 30-31 reserved */
235 /* Bits 6-7 reserved */
236 [X_MAX_LIM] = GENMASK(13, 8),
237 /* Bits 14-15 reserved */
239 /* Bits 22-23 reserved */
241 /* Bits 30-31 reserved */
249 /* Bits 6-7 reserved */
250 [X_MAX_LIM] = GENMASK(13, 8),
251 /* Bits 14-15 reserved */
253 /* Bits 22-23 reserved */
255 /* Bits 30-31 reserved */
263 /* Bits 6-7 reserved */
264 [X_MAX_LIM] = GENMASK(13, 8),
265 /* Bits 14-15 reserved */
267 /* Bits 22-23 reserved */
269 /* Bits 30-31 reserved */
276 [FRAG_OFFLOAD_EN] = BIT(0),
279 /* Bit 7 reserved */
280 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
281 /* Bits 9-31 reserved */
288 /* Bits 2-31 reserved */
295 [HDR_OFST_METADATA_VALID] = BIT(6),
297 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
298 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
300 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
308 [HDR_ENDIANNESS] = BIT(0),
309 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
310 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
311 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
313 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
314 /* Bits 14-15 reserved */
318 /* Bits 22-31 reserved */
328 [DCPH_ENABLE] = BIT(3),
330 /* Bits 9-11 reserved */
332 [PIPE_REPLICATION_EN] = BIT(28),
333 [PAD_EN] = BIT(29),
334 [DRBIP_ACL_ENABLE] = BIT(30),
335 /* Bit 31 reserved */
344 /* Bit 11 reserved */
347 [SW_EOF_ACTIVE] = BIT(23),
348 [FORCE_CLOSE] = BIT(24),
349 /* Bit 25 reserved */
350 [HARD_BYTE_LIMIT_EN] = BIT(26),
351 [AGGR_GRAN_SEL] = BIT(27),
352 /* Bits 28-31 reserved */
358 [HOL_BLOCK_EN] = BIT(0),
359 /* Bits 1-31 reserved */
367 /* Bits 5-7 reserved */
368 [TIMER_GRAN_SEL] = BIT(8),
369 /* Bits 9-31 reserved */
377 [SYSPIPE_ERR_DETECTION] = BIT(6),
378 [PACKET_OFFSET_VALID] = BIT(7),
379 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
380 [IGNORE_MIN_PKT_ERR] = BIT(14),
381 /* Bit 15 reserved */
389 /* Bits 2-31 reserved */
397 /* Bits 8-31 reserved */
403 [STATUS_EN] = BIT(0),
405 /* Bits 6-8 reserved */
406 [STATUS_PKT_SUPPRESS] = BIT(9),
407 /* Bits 10-31 reserved */
413 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
414 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
415 [FILTER_HASH_MSK_DST_IP] = BIT(2),
416 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
417 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
418 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
419 [FILTER_HASH_MSK_METADATA] = BIT(6),
421 /* Bits 7-15 reserved */
422 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
423 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
424 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
425 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
426 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
427 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
428 [ROUTER_HASH_MSK_METADATA] = BIT(22),
430 /* Bits 23-31 reserved */
446 [UC_INTR] = BIT(0),
447 /* Bits 1-31 reserved */
452 /* Valid bits defined by ipa->available */
455 /* Valid bits defined by ipa->available */
458 /* Valid bits defined by ipa->available */