Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 /* Bit 4 reserved */
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
20 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
21 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
22 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
23 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
24 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
25 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
26 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
27 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
29 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
30 /* Bits 22-31 reserved */
36 [CLKON_RX] = BIT(0),
37 [CLKON_PROC] = BIT(1),
38 [TX_WRAPPER] = BIT(2),
39 [CLKON_MISC] = BIT(3),
40 [RAM_ARB] = BIT(4),
41 [FTCH_HPS] = BIT(5),
42 [FTCH_DPS] = BIT(6),
43 [CLKON_HPS] = BIT(7),
44 [CLKON_DPS] = BIT(8),
45 [RX_HPS_CMDQS] = BIT(9),
46 [HPS_DPS_CMDQS] = BIT(10),
47 [DPS_TX_CMDQS] = BIT(11),
48 [RSRC_MNGR] = BIT(12),
49 [CTX_HANDLER] = BIT(13),
50 [ACK_MNGR] = BIT(14),
51 [D_DCPH] = BIT(15),
52 [H_DCPH] = BIT(16),
53 [CLKON_DCMP] = BIT(17),
54 [NTF_TX_CMDQS] = BIT(18),
55 [CLKON_TX_0] = BIT(19),
56 [CLKON_TX_1] = BIT(20),
57 [CLKON_FNR] = BIT(21),
58 [QSB2AXI_CMDQ_L] = BIT(22),
59 [AGGR_WRAPPER] = BIT(23),
60 [RAM_SLAVEWAY] = BIT(24),
61 [CLKON_QMB] = BIT(25),
62 [WEIGHT_ARB] = BIT(26),
63 [GSI_IF] = BIT(27),
64 [CLKON_GLOBAL] = BIT(28),
65 [GLOBAL_2X_CLK] = BIT(29),
66 [DPL_FIFO] = BIT(30),
67 /* Bit 31 reserved */
73 [ROUTE_DIS] = BIT(0),
75 [ROUTE_DEF_HDR_TABLE] = BIT(6),
78 /* Bits 22-23 reserved */
79 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
80 /* Bits 25-31 reserved */
95 /* Bits 8-31 reserved */
103 /* Bits 8-15 reserved */
111 [IPV6_ROUTER_HASH] = BIT(0),
112 /* Bits 1-3 reserved */
113 [IPV6_FILTER_HASH] = BIT(4),
114 /* Bits 5-7 reserved */
115 [IPV4_ROUTER_HASH] = BIT(8),
116 /* Bits 9-11 reserved */
117 [IPV4_FILTER_HASH] = BIT(12),
118 /* Bits 13-31 reserved */
124 [IPV6_ROUTER_HASH] = BIT(0),
125 /* Bits 1-3 reserved */
126 [IPV6_FILTER_HASH] = BIT(4),
127 /* Bits 5-7 reserved */
128 [IPV4_ROUTER_HASH] = BIT(8),
129 /* Bits 9-11 reserved */
130 [IPV4_FILTER_HASH] = BIT(12),
131 /* Bits 13-31 reserved */
136 /* Valid bits defined by ipa->available */
141 /* Bits 18-31 reserved */
147 /* Valid bits defined by ipa->available */
151 /* Bits 0-1 reserved */
154 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
155 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
156 [PA_MASK_EN] = BIT(12),
157 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
158 [DUAL_TX_ENABLE] = BIT(17),
159 /* Bits 18-31 reserved */
166 /* Bits 4-7 reserved */
168 /* Bits 13-15 reserved */
170 /* Bits 21-23 reserved */
172 /* Bits 28-31 reserved */
179 [CONST_NON_IDLE_ENABLE] = BIT(16),
180 /* Bits 17-31 reserved */
187 /* Bits 5-6 reserved */
188 [DPL_TIMESTAMP_SEL] = BIT(7),
190 /* Bits 13-15 reserved */
192 /* Bits 21-31 reserved */
199 /* Bits 9-30 reserved */
200 [DIV_ENABLE] = BIT(31),
215 /* Bits 6-7 reserved */
216 [X_MAX_LIM] = GENMASK(13, 8),
217 /* Bits 14-15 reserved */
219 /* Bits 22-23 reserved */
221 /* Bits 30-31 reserved */
229 /* Bits 6-7 reserved */
230 [X_MAX_LIM] = GENMASK(13, 8),
231 /* Bits 14-15 reserved */
233 /* Bits 22-23 reserved */
235 /* Bits 30-31 reserved */
243 /* Bits 6-7 reserved */
244 [X_MAX_LIM] = GENMASK(13, 8),
245 /* Bits 14-15 reserved */
247 /* Bits 22-23 reserved */
249 /* Bits 30-31 reserved */
257 /* Bits 6-7 reserved */
258 [X_MAX_LIM] = GENMASK(13, 8),
259 /* Bits 14-15 reserved */
261 /* Bits 22-23 reserved */
263 /* Bits 30-31 reserved */
271 /* Bits 6-7 reserved */
272 [X_MAX_LIM] = GENMASK(13, 8),
273 /* Bits 14-15 reserved */
275 /* Bits 22-23 reserved */
277 /* Bits 30-31 reserved */
285 /* Bits 6-7 reserved */
286 [X_MAX_LIM] = GENMASK(13, 8),
287 /* Bits 14-15 reserved */
289 /* Bits 22-23 reserved */
291 /* Bits 30-31 reserved */
298 [FRAG_OFFLOAD_EN] = BIT(0),
301 /* Bit 7 reserved */
302 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
303 /* Bits 9-31 reserved */
310 /* Bits 2-31 reserved */
317 [HDR_OFST_METADATA_VALID] = BIT(6),
319 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
320 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
322 [HDR_A5_MUX] = BIT(26),
323 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
331 [HDR_ENDIANNESS] = BIT(0),
332 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
333 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
334 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
336 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
337 /* Bits 14-15 reserved */
341 /* Bits 22-31 reserved */
351 [DCPH_ENABLE] = BIT(3),
353 /* Bits 9-11 reserved */
355 [PIPE_REPLICATION_EN] = BIT(28),
356 [PAD_EN] = BIT(29),
357 /* Bits 30-31 reserved */
366 /* Bit 11 reserved */
369 [SW_EOF_ACTIVE] = BIT(23),
370 [FORCE_CLOSE] = BIT(24),
371 /* Bit 25 reserved */
372 [HARD_BYTE_LIMIT_EN] = BIT(26),
373 [AGGR_GRAN_SEL] = BIT(27),
374 /* Bits 28-31 reserved */
380 [HOL_BLOCK_EN] = BIT(0),
381 /* Bits 1-31 reserved */
389 /* Bits 5-7 reserved */
390 [TIMER_GRAN_SEL] = BIT(8),
391 /* Bits 9-31 reserved */
399 [SYSPIPE_ERR_DETECTION] = BIT(6),
400 [PACKET_OFFSET_VALID] = BIT(7),
401 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
402 [IGNORE_MIN_PKT_ERR] = BIT(14),
403 /* Bit 15 reserved */
411 /* Bits 3-31 reserved */
419 /* Bits 8-31 reserved */
425 [STATUS_EN] = BIT(0),
427 /* Bits 6-8 reserved */
428 [STATUS_PKT_SUPPRESS] = BIT(9),
429 /* Bits 10-31 reserved */
435 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
436 [FILTER_HASH_MSK_SRC_IP] = BIT(1),
437 [FILTER_HASH_MSK_DST_IP] = BIT(2),
438 [FILTER_HASH_MSK_SRC_PORT] = BIT(3),
439 [FILTER_HASH_MSK_DST_PORT] = BIT(4),
440 [FILTER_HASH_MSK_PROTOCOL] = BIT(5),
441 [FILTER_HASH_MSK_METADATA] = BIT(6),
443 /* Bits 7-15 reserved */
444 [ROUTER_HASH_MSK_SRC_ID] = BIT(16),
445 [ROUTER_HASH_MSK_SRC_IP] = BIT(17),
446 [ROUTER_HASH_MSK_DST_IP] = BIT(18),
447 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19),
448 [ROUTER_HASH_MSK_DST_PORT] = BIT(20),
449 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21),
450 [ROUTER_HASH_MSK_METADATA] = BIT(22),
452 /* Bits 23-31 reserved */
468 [UC_INTR] = BIT(0),
469 /* Bits 1-31 reserved */
474 /* Valid bits defined by ipa->available */
477 /* Valid bits defined by ipa->available */
480 /* Valid bits defined by ipa->available */