Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
11 /* Bit 0 reserved */
12 [GSI_SNOC_BYPASS_DIS] = BIT(1),
13 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
14 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
15 [IPA_DCMP_FAST_CLK_EN] = BIT(4),
16 [IPA_QMB_SELECT_CONS_EN] = BIT(5),
17 [IPA_QMB_SELECT_PROD_EN] = BIT(6),
18 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
19 [GSI_MULTI_INORDER_WR_DIS] = BIT(8),
20 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
21 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
22 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
23 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
24 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
25 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
26 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
27 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
29 /* Bits 21-31 reserved */
35 [CLKON_RX] = BIT(0),
36 [CLKON_PROC] = BIT(1),
37 [TX_WRAPPER] = BIT(2),
38 [CLKON_MISC] = BIT(3),
39 [RAM_ARB] = BIT(4),
40 [FTCH_HPS] = BIT(5),
41 [FTCH_DPS] = BIT(6),
42 [CLKON_HPS] = BIT(7),
43 [CLKON_DPS] = BIT(8),
44 [RX_HPS_CMDQS] = BIT(9),
45 [HPS_DPS_CMDQS] = BIT(10),
46 [DPS_TX_CMDQS] = BIT(11),
47 [RSRC_MNGR] = BIT(12),
48 [CTX_HANDLER] = BIT(13),
49 [ACK_MNGR] = BIT(14),
50 [D_DCPH] = BIT(15),
51 [H_DCPH] = BIT(16),
52 /* Bit 17 reserved */
53 [NTF_TX_CMDQS] = BIT(18),
54 [CLKON_TX_0] = BIT(19),
55 [CLKON_TX_1] = BIT(20),
56 [CLKON_FNR] = BIT(21),
57 [QSB2AXI_CMDQ_L] = BIT(22),
58 [AGGR_WRAPPER] = BIT(23),
59 [RAM_SLAVEWAY] = BIT(24),
60 [CLKON_QMB] = BIT(25),
61 [WEIGHT_ARB] = BIT(26),
62 [GSI_IF] = BIT(27),
63 [CLKON_GLOBAL] = BIT(28),
64 [GLOBAL_2X_CLK] = BIT(29),
65 /* Bits 30-31 reserved */
71 [ROUTE_DIS] = BIT(0),
73 [ROUTE_DEF_HDR_TABLE] = BIT(6),
76 /* Bits 22-23 reserved */
77 [ROUTE_DEF_RETAIN_HDR] = BIT(24),
78 /* Bits 25-31 reserved */
93 /* Bits 8-31 reserved */
101 /* Bits 8-15 reserved */
109 [IPV6_ROUTER_HASH] = BIT(0),
110 /* Bits 1-3 reserved */
111 [IPV6_FILTER_HASH] = BIT(4),
112 /* Bits 5-7 reserved */
113 [IPV4_ROUTER_HASH] = BIT(8),
114 /* Bits 9-11 reserved */
115 [IPV4_FILTER_HASH] = BIT(12),
116 /* Bits 13-31 reserved */
122 [IPV6_ROUTER_HASH] = BIT(0),
123 /* Bits 1-3 reserved */
124 [IPV6_FILTER_HASH] = BIT(4),
125 /* Bits 5-7 reserved */
126 [IPV4_ROUTER_HASH] = BIT(8),
127 /* Bits 9-11 reserved */
128 [IPV4_FILTER_HASH] = BIT(12),
129 /* Bits 13-31 reserved */
134 /* Valid bits defined by ipa->available */
141 /* Bits 17-31 reserved */
147 /* Valid bits defined by ipa->available */
151 /* Bits 0-3 reserved */
153 /* Bits 9-31 reserved */
159 /* Bits 0-1 reserved */
162 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10),
163 [DMAW_MAX_BEATS_256_DIS] = BIT(11),
164 [PA_MASK_EN] = BIT(12),
165 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13),
166 /* Bit 17 reserved */
167 [SSPND_PA_NO_START_STATE] = BIT(18),
168 [SSPND_PA_NO_BQ_STATE] = BIT(19),
169 /* Bits 20-31 reserved */
176 /* Bits 4-7 reserved */
178 /* Bits 13-15 reserved */
180 /* Bits 21-23 reserved */
182 /* Bits 28-31 reserved */
189 [CONST_NON_IDLE_ENABLE] = BIT(16),
190 /* Bits 17-31 reserved */
197 /* Bits 6-7 reserved */
198 [X_MAX_LIM] = GENMASK(13, 8),
199 /* Bits 14-15 reserved */
201 /* Bits 22-23 reserved */
203 /* Bits 30-31 reserved */
211 /* Bits 6-7 reserved */
212 [X_MAX_LIM] = GENMASK(13, 8),
213 /* Bits 14-15 reserved */
215 /* Bits 22-23 reserved */
217 /* Bits 30-31 reserved */
225 /* Bits 6-7 reserved */
226 [X_MAX_LIM] = GENMASK(13, 8),
227 /* Bits 14-15 reserved */
229 /* Bits 22-23 reserved */
231 /* Bits 30-31 reserved */
239 /* Bits 6-7 reserved */
240 [X_MAX_LIM] = GENMASK(13, 8),
241 /* Bits 14-15 reserved */
243 /* Bits 22-23 reserved */
245 /* Bits 30-31 reserved */
252 [FRAG_OFFLOAD_EN] = BIT(0),
255 /* Bit 7 reserved */
256 [CS_GEN_QMB_MASTER_SEL] = BIT(8),
257 /* Bits 9-31 reserved */
264 /* Bits 2-31 reserved */
271 [HDR_OFST_METADATA_VALID] = BIT(6),
273 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13),
274 [HDR_OFST_PKT_SIZE_VALID] = BIT(19),
276 [HDR_A5_MUX] = BIT(26),
277 [HDR_LEN_INC_DEAGG_HDR] = BIT(27),
278 [HDR_METADATA_REG_VALID] = BIT(28),
279 /* Bits 29-31 reserved */
285 [HDR_ENDIANNESS] = BIT(0),
286 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1),
287 [HDR_TOTAL_LEN_OR_PAD] = BIT(2),
288 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3),
290 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10),
291 /* Bits 14-31 reserved */
301 /* Bit 3 reserved */
303 /* Bits 9-11 reserved */
305 [PIPE_REPLICATION_EN] = BIT(28),
306 [PAD_EN] = BIT(29),
307 [HDR_FTCH_DISABLE] = BIT(30),
308 /* Bit 31 reserved */
319 [SW_EOF_ACTIVE] = BIT(21),
320 [FORCE_CLOSE] = BIT(22),
321 /* Bit 23 reserved */
322 [HARD_BYTE_LIMIT_EN] = BIT(24),
323 /* Bits 25-31 reserved */
329 [HOL_BLOCK_EN] = BIT(0),
330 /* Bits 1-31 reserved */
338 /* Bits 5-7 reserved */
340 /* Bits 9-31 reserved */
348 [SYSPIPE_ERR_DETECTION] = BIT(6),
349 [PACKET_OFFSET_VALID] = BIT(7),
350 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8),
351 [IGNORE_MIN_PKT_ERR] = BIT(14),
352 /* Bit 15 reserved */
359 [ENDP_RSRC_GRP] = BIT(0),
360 /* Bits 1-31 reserved */
369 /* Bits 16-31 reserved */
375 [STATUS_EN] = BIT(0),
377 /* Bits 6-7 reserved */
378 [STATUS_LOCATION] = BIT(8),
379 [STATUS_PKT_SUPPRESS] = BIT(9),
380 /* Bits 10-31 reserved */
395 [UC_INTR] = BIT(0),
396 /* Bits 1-31 reserved */
401 /* Valid bits defined by ipa->available */
404 /* Valid bits defined by ipa->available */
407 /* Valid bits defined by ipa->available */