Lines Matching +full:13 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
9 #define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
10 #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
11 #define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
12 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
13 #define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
14 #define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
15 #define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
16 #define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
17 #define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9)
18 #define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10)
19 #define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11)
20 #define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12)
21 #define MTK_PPE_GLO_CFG_BUSY BIT(31)
24 #define MTK_PPE_MD_TOAP_BYP_CRSN0 BIT(1)
25 #define MTK_PPE_MD_TOAP_BYP_CRSN1 BIT(2)
26 #define MTK_PPE_MD_TOAP_BYP_CRSN2 BIT(3)
27 #define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6)
28 #define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7)
29 #define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8)
30 #define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9)
31 #define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10)
32 #define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12)
33 #define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13)
34 #define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14)
35 #define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15)
36 #define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16)
37 #define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17)
38 #define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18)
39 #define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19)
40 #define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20)
48 #define MTK_PPE_TB_CFG_ENTRY_80B BIT(3)
50 #define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6)
51 #define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7)
52 #define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8)
53 #define MTK_PPE_TB_CFG_AGE_TCP BIT(9)
54 #define MTK_PPE_TB_CFG_AGE_UDP BIT(10)
55 #define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11)
56 #define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)
60 #define MTK_PPE_TB_CFG_INFO_SEL BIT(20)
83 #define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
90 #define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)
94 #define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)
124 #define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)
128 #define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)
134 #define MTK_PPE_CACHE_CTL_EN BIT(0)
135 #define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4)
136 #define MTK_PPE_CACHE_CTL_REQ BIT(8)
137 #define MTK_PPE_CACHE_CTL_CLEAR BIT(9)
138 #define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12)
141 #define MTK_PPE_MIB_CFG_EN BIT(0)
142 #define MTK_PPE_MIB_CFG_RD_CLR BIT(1)
147 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
148 #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)