Lines Matching +full:13 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
73 # define V3D_CTSEMA BIT(12)
74 # define V3D_CTRTSD BIT(8)
75 # define V3D_CTRUN BIT(5)
76 # define V3D_CTSUBS BIT(4)
77 # define V3D_CTERR BIT(3)
78 # define V3D_CTMODE BIT(0)
97 # define V3D_BMOOM BIT(8)
98 # define V3D_RMBUSY BIT(3)
99 # define V3D_RMACTIVE BIT(2)
100 # define V3D_BMBUSY BIT(1)
101 # define V3D_BMACTIVE BIT(0)
121 # define V3D_PCTRE_EN BIT(31)
144 # define PV_CONTROL_CLR_AT_START BIT(14)
145 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
146 # define PV_CONTROL_WAIT_HSTART BIT(12)
154 # define PV_CONTROL_FIFO_CLR BIT(1)
155 # define PV_CONTROL_EN BIT(0)
160 # define PV_VCONTROL_ODD_FIRST BIT(5)
161 # define PV_VCONTROL_INTERLACE BIT(4)
162 # define PV_VCONTROL_DSI BIT(3)
163 # define PV_VCONTROL_COMMAND BIT(2)
164 # define PV_VCONTROL_CONTINUOUS BIT(1)
165 # define PV_VCONTROL_VIDEN BIT(0)
198 # define PV_INT_VID_IDLE BIT(9)
199 # define PV_INT_VFP_END BIT(8)
200 # define PV_INT_VFP_START BIT(7)
201 # define PV_INT_VACT_START BIT(6)
202 # define PV_INT_VBP_START BIT(5)
203 # define PV_INT_VSYNC_START BIT(4)
204 # define PV_INT_HFP_START BIT(3)
205 # define PV_INT_HACT_START BIT(2)
206 # define PV_INT_HBP_START BIT(1)
207 # define PV_INT_HSYNC_START BIT(0)
222 # define SCALER_DISPCTRL_ENABLE BIT(31)
230 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
231 /* Enables Display 0 end-of-line-N contribution to
234 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
236 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
238 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
239 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
240 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
244 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
246 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
256 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
258 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
262 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
266 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
270 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
272 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
274 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
278 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
280 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
282 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
286 # define SCALER_DISPSTAT_IRQDMA BIT(4)
288 * corresponding interrupt bit is enabled in DISPCTRL.
290 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
292 # define SCALER_DISPSTAT_IRQSCL BIT(0)
314 (x) * (SCALER_DISPLIST1 - \
321 (x) * (SCALER_DISPLACT1 - \
325 # define SCALER_DISPCTRLX_ENABLE BIT(31)
326 # define SCALER_DISPCTRLX_RESET BIT(30)
330 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
334 # define SCALER_DISPCTRLX_ONECTX BIT(28)
336 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
340 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
352 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
356 # define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
357 # define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
362 # define SCALER_DISPBKGND_AUTOHS BIT(31)
363 # define SCALER_DISPBKGND_INTERLACE BIT(30)
364 # define SCALER_DISPBKGND_GAMMA BIT(29)
371 # define SCALER_DISPBKGND_FILL BIT(24)
380 # define SCALER_DISPSTATX_FULL BIT(29)
381 # define SCALER_DISPSTATX_EMPTY BIT(28)
387 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
393 * channel. Must be 4-pixel aligned.
401 (x) * (SCALER_DISPBKGND1 - \
410 (x) * (SCALER_DISPSTAT1 - \
415 (x) * (SCALER_DISPBASE1 - \
419 (x) * (SCALER_DISPCTRL1 - \
430 # define SCALER_GAMADDR_AUTOINC BIT(31)
434 # define SCALER_GAMADDR_SRAMENB BIT(30)
438 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
448 /* Offsets are 8-bit 2s-complement. */
487 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
488 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
490 # define SCALER_DISPSLAVE_EOL BIT(26)
492 # define SCALER_DISPSLAVE_EMPTY BIT(25)
494 # define SCALER_DISPSLAVE_VALID BIT(24)
504 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
505 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
507 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
509 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
510 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
514 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
515 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
516 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
517 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
518 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
521 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
523 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
552 VC4_HDMI_MAI_SAMPLE_RATE_128000 = 13,
557 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
562 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
564 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
568 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
572 # define VC4_HDMI_HORZA_VPOS BIT(14)
573 # define VC4_HDMI_HORZA_HPOS BIT(13)
578 /* Horizontal pack porch (htotal - hsync_end). */
581 /* Horizontal sync pulse (hsync_end - hsync_start). */
584 /* Horizontal front porch (hsync_start - hdisplay). */
588 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
589 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
590 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
591 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
592 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
593 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
594 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
595 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
596 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
597 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
600 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
601 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
602 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
603 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
604 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
606 /* Vertical sync pulse (vsync_end - vsync_start). */
609 /* Vertical front porch (vsync_start - vdisplay). */
610 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
611 # define VC4_HDMI_VERTA_VFP_SHIFT 13
619 /* Vertical pack porch (vtotal - vsync_end). */
624 # define VC4_HDMI_CEC_TX_EOM BIT(31)
629 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
630 # define VC4_HDMI_CEC_RX_EOM BIT(29)
631 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
642 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
643 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
645 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
649 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
655 /* Divides off of HSM clock to generate CEC bit clock. */
656 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
660 /* Set these fields to how many bit clock cycles get to that many
692 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
693 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
694 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
695 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
696 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
704 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
706 # define VC4_HDMI_CPU_CEC BIT(6)
707 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
710 # define VC4_HD_CECRXD BIT(9)
712 # define VC4_HD_CECOVR BIT(8)
715 # define VC4_HD_M_SW_RST BIT(2)
716 # define VC4_HD_M_ENABLE BIT(0)
721 # define VC4_HD_MAI_CTL_DLATE BIT(15)
722 # define VC4_HD_MAI_CTL_BUSY BIT(14)
723 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
724 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
725 # define VC4_HD_MAI_CTL_FULL BIT(11)
726 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
727 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
728 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
731 # define VC4_HD_MAI_CTL_PAREN BIT(8)
734 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
735 /* Underflow error status bit, write 1 to clear. */
736 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
737 /* Overflow error status bit, write 1 to clear. */
738 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
739 /* Single-shot reset bit. Read value is undefined. */
740 # define VC4_HD_MAI_CTL_RESET BIT(0)
746 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
759 # define VC4_HD_VID_CTL_ENABLE BIT(31)
760 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
761 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
762 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
763 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
764 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
765 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
766 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
776 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
782 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
783 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
785 # define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
790 # define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
791 # define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
799 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
828 HVS_PIXEL_FORMAT_PALETTE = 13,
853 #define SCALER_CTL0_END BIT(31)
854 #define SCALER_CTL0_VALID BIT(30)
866 #define SCALER_CTL0_ALPHA_MASK BIT(19)
867 #define SCALER_CTL0_HFLIP BIT(16)
868 #define SCALER_CTL0_VFLIP BIT(15)
877 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
878 #define SCALER_CTL0_ORDER_SHIFT 13
887 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
889 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
907 #define SCALER_CTL0_UNITY BIT(4)
908 #define SCALER5_CTL0_UNITY BIT(15)
927 #define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
930 #define SCALER5_POS0_VFLIP BIT(31)
931 #define SCALER5_POS0_HFLIP BIT(15)
940 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
942 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
944 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
949 #define SCALER5_CTL2_GAMMA BIT(16)
972 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
973 #define SCALER_POS2_ALPHA_MIX BIT(28)
989 * 0x2: 2, 0x3: -1}
997 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
1000 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1045 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1056 #define SCALER_PPF_NOINTERP BIT(31)
1060 #define SCALER_PPF_AGC BIT(30)
1066 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1068 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1084 /* PITCH0 fields for T-tiled. */
1087 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1088 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1090 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)